欢迎访问ic37.com |
会员登录 免费注册
发布采购

CS8900A-IQ3 参数 Datasheet PDF下载

CS8900A-IQ3图片预览
型号: CS8900A-IQ3
PDF下载: 下载PDF文件 查看货源
内容描述: 水晶局域网? ISA以太网控制器 [Crystal LAN ⑩ ISA Ethernet Controller]
分类和应用: 控制器局域网以太网
文件页数/大小: 128 页 / 1360 K
品牌: CIRRUS [ CIRRUS LOGIC ]
 浏览型号CS8900A-IQ3的Datasheet PDF文件第75页浏览型号CS8900A-IQ3的Datasheet PDF文件第76页浏览型号CS8900A-IQ3的Datasheet PDF文件第77页浏览型号CS8900A-IQ3的Datasheet PDF文件第78页浏览型号CS8900A-IQ3的Datasheet PDF文件第80页浏览型号CS8900A-IQ3的Datasheet PDF文件第81页浏览型号CS8900A-IQ3的Datasheet PDF文件第82页浏览型号CS8900A-IQ3的Datasheet PDF文件第83页  
CS8900A  
Crystal LAN™ ISA Ethernet Controller  
5.0 OPERATION  
The ISQ is read as a 16-bit word. The lower six bits  
(0 through 5) contain the register number (4, 8, C,  
10, or 12). The upper ten bits (6 through F) contain  
the register contents. The host must always read the  
entire 16-bit word.  
5.1 Managing Interrupts and Servicing the  
Interrupt Status Queue  
The Interrupt Status Queue (ISQ) is used by the  
CS8900A to communicate Event reports to the host  
processor. Whenever an event occurs that triggers The active interrupt pin (INTRQx) is selected via  
an enabled interrupt, the CS8900A sets the appro- the Interrupt Number register (PacketPage base +  
priate bit(s) in one of five registers, maps the con- 22h). As an additional option, all of the interrupt  
tents of that register to the ISQ, and drives the  
selected interrupt request pin high (if an earlier in-  
terrupt is waiting in the queue, the interrupt request  
pin will already be high). When the host services  
the interrupt, it must first read the ISQ to learn the  
nature of the interrupt. It can then process the inter-  
rupt (the first read to the ISQ causes the interrupt  
request pin to go low.)  
pins can be 3-Stated using the same register. see  
Section 4.3 on page 42.  
An event triggers an interrupt only when the En-  
ableIRQ bit of the Bus Control register (bit F of  
register 17) is set. After the CS8900A has generat-  
ed an interrupt, the first read of the ISQ makes the  
INTRQ output pin go low (inactive). INTRQ re-  
mains low until the null word (0000h) is read from  
the ISQ, or for 1.6us, whichever is longer.  
Three of the registers mapped to the ISQ are event  
registers: RxEvent (Register 4), TxEvent (Register  
8), and BufEvent (Register C). The other two reg-  
isters are counter-overflow reports: RxMISS (Reg-  
ister 10) and TxCOL (Register 12). There may be  
more than one RxEvent report and/or more than  
5.2 Basic Receive Operation  
5.2.0.1 Overview  
Once an incoming packet has passed through the  
analog front end and Manchester decoder, it goes  
one TxEvent report in the ISQ at a time. However, through the following three-step receive process:  
there may be only one BufEvent report, one Rx-  
MISS report and one TxCOL report in the ISQ at a  
time.  
1) Pre-Processing  
2) Temporary Buffering  
3) Transfer to Host  
Event reports stored in the ISQ are read out in the  
order of priority, with RxEvent first, followed by Figure 20 shows the steps in frame reception.  
TxEvent, BufEvent, RxMiss, and then TxCOL.  
As shown in the figure, all receive frames go  
The host only needs to read from one location to get  
through the same pre-processing and temporary  
the interrupt currently at the front of the queue. In  
buffering phases, regardless of transfer method  
Memory Mode, the ISQ is located at PacketPage  
Once a frame has been pre-processed and buffered,  
base + 0120h. In I/O Mode, it is located at I/O base  
it can be accessed by the host in either Memory or  
+ 0008h. Each time the host reads the ISQ, the bits  
I/O space. In addition, the CS8900A can transfer  
in the corresponding register are cleared and the  
receive frames to host memory via host DMA. This  
next report in the queue moves to the front.  
section describes receive frame pre-processing and  
When the host starts reading the ISQ, it must read  
Memory and I/O space receive operation.  
and process all Event reports in the queue. A read-  
Section 5.4 on page 90 through Section 5.5 on  
out of a null word (0000h) indicates that all inter-  
page 93 describe DMA operation.  
rupts have been read.  
CIRRUS LOGIC PRODUCT DATA SHEET  
DS271PP3  
79  
 
 复制成功!