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CS8900A-IQ3 参数 Datasheet PDF下载

CS8900A-IQ3图片预览
型号: CS8900A-IQ3
PDF下载: 下载PDF文件 查看货源
内容描述: 水晶局域网? ISA以太网控制器 [Crystal LAN ⑩ ISA Ethernet Controller]
分类和应用: 控制器局域网以太网
文件页数/大小: 128 页 / 1360 K
品牌: CIRRUS [ CIRRUS LOGIC ]
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CS8900A  
Crystal LAN™ ISA Ethernet Controller  
4.4.9 Register 7: Transmit Configuration  
(TxCFG, Read/Write, Address: PacketPage base + 0106h)  
7
6
5
4
3
2
1
0
SQE erroriE Loss-of-CRSiE  
000111  
F
E
D
C
B
A
9
8
16colliE  
AnycolliE  
JabberiE  
Out-of-window  
TxOKiE  
Each bit in TxCFG is an interrupt enable. When set, the interrupt is enabled as described below. When clear, there  
is no interrupt.  
000111  
These bits provide an internal address used by the CS8900A to identify this as the Transmit  
Configuration Register.  
Loss-of-CRSiE  
If the CS8900A starts transmitting on the AUI and does not see the Carrier Sense signal at the  
end of the preamble, an interrupt is generated if this bit is set. Carrier Sense activity is reported  
by the CRS bit (Register 14, LineST, Bit E).  
SQErroriE  
When set, an interrupt is generated if there is an SQE error. (At the end of a transmission on  
the AUI, the CS8900A expects to see a collision within 64 bit times. If this does not happen,  
there is an SQE error.)  
TxOKiE  
When set, an interrupt is generated if a packet is completely transmitted.  
Out-of-windowiE  
When set, an interrupt is generated if a late collision occurs (a late collision is a collision which  
occurs after the first 512 bit times). When this occurs, the CS8900A forces a bad CRC and ter-  
minates the transmission.  
JabberiE  
AnycolliE  
When set, an interrupt is generated if a transmission is longer than approximately 26 ms.  
When set, if one or more collisions occur during the transmission of a packet, an interrupt oc-  
curs at the end of the transmission  
16colliE  
If the CS8900A encounters 16 normal collisions while attempting to transmit a particular packet,  
the CS8900A stops attempting to transmit that packet. When this bit is set, there is an interrupt  
upon detecting the 16th collision.  
After reset, if no EEPROM is found by the CS8900A, then the register has the following initial state. If an EEPROM  
is found, then the register’s initial value may be set by the EEPROM. See Section 3.3 on page 19.  
Reset value is: 0000 0000 0000 0111  
Notes: Bit 8 (TxOKiE) and Bit B (AnycolliE) are interrupts for normal transmit operation. Bits 6, 7, 9, A, and FNotes:  
are interrupts for abnormal transmit operation.  
CIRRUS LOGIC PRODUCT DATA SHEET  
56  
DS271PP3  
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