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CS8900A-IQ3 参数 Datasheet PDF下载

CS8900A-IQ3图片预览
型号: CS8900A-IQ3
PDF下载: 下载PDF文件 查看货源
内容描述: 水晶局域网? ISA以太网控制器 [Crystal LAN ⑩ ISA Ethernet Controller]
分类和应用: 控制器局域网以太网
文件页数/大小: 128 页 / 1360 K
品牌: CIRRUS [ CIRRUS LOGIC ]
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CS8900A  
Crystal LAN™ ISA Ethernet Controller  
4.4.7 Register 4: Receiver Event  
(RxEvent, Read-only, Address: PacketPage base + 0124h)  
7
6
5
4
3
2
1
0
Dribblebits  
IAHash  
000100  
F
E
D
C
B
A
9
8
Extradata  
Runt  
CRCerror  
Broadcast  
Individual Adr  
Hashed  
RxOK  
Alternate meaning if bits 8 and 9 are both set (see Section 5.3 on page 87 for exception regarding Broadcast  
frames).  
7
6
5
4
3
2
1
0
Dribblebits  
IAHash  
000100  
F
E
D
C
B
A
9
8
Hash Table Index (see Section 5.3 on page 87)  
Hashed = 1  
RxOK = 1  
RxEvent reports the status of the current received frame.  
000100  
IAHash  
These bits identify this as the Receiver Event Register. When reading this register, these bits  
will be 000100, where the LSB corresponds to Bit 0.  
If the received frame’s Destination Address is accepted by the hash filter, then this bit is set if,  
and only if IAHashA (Register 5, RxCTL, Bit 6) is set, and Hashed (Bit 9) is set. See Section 5.3  
on page 87.  
Dribblebits  
RxOK  
If set, the received frame had from one to seven bits after the last received full byte. An "Align-  
ment Error" occurs when Dribblebits and CRCerror (Bit C) are both set.  
If set, the received frame had a good CRC and valid length (i.e., there is not a CRC error, Runt  
error, or Extradata error). When RxOK is set, then the length of the received frame is contained  
at PacketPage base + 0402h. If RxOKiE (Register 3, RxCFG, Bit 8) is set, there is an interrupt.  
Hashed  
If set, the received frame had a Destination Address that was accepted by the hash filter. If  
Hashed and RxOK (Bit 8) are set, Bits F through A of RxEvent become the Hash Table Index  
for this frame [See Section 5.3 on page 87 for an exception regarding broadcast frames!].If  
Hashed and RxOK are not both set, then Bits F through A are individual event bits as defined  
below.  
IndividualAdr  
Broadcast  
If the received frame had a Destination Address which matched the Individual Address found  
at PacketPage base + 0158h, then this bit is set if, and only if, RxOK (Bit 8) is set and Individ-  
ualA (Register 5, RxCTL, Bit A) is set.  
If the received frame had a Broadcast Address (FFFF FFFF FFFFh) as the Destination Ad-  
dress, then this bit is set if, and only if, RxOK is set and BroadcastA (Register 5, RxCTL, Bit B)  
is set.  
CRCerror  
Runt  
If set, the received frame had a bad CRC. If CRCerroriE (Register 3, RxCFG, Bit C) is set, there  
is an interrupt  
If set, the received frame was shorter than 64 bytes. If RuntiE (Register 3, RxCFG, Bit D) is set,  
there is an interrupt.  
Extradata  
If set, the received frame was longer than 1518 bytes. All bytes beyond 1518 are discarded. If  
ExtradataiE (Register 3, RxCFG, Bit E) is set, there is an interrupt.  
Reset value is: 0000 0000 0000 0100  
Notes: 3. All RxEvent bits are cleared upon readout. The host is responsible for processing all event bits.  
4. RxStatus register (PacketPage base + 0400h) is the same as the RxEvent register except RxStatus is  
not cleared when RxEvent is read. See Section 5.2 on page 79. The value in the RxEvent register is  
undefined when RxDMAOnly bit (Bit 9, Register 3, RxCFG) is set.  
CIRRUS LOGIC PRODUCT DATA SHEET  
54  
DS271PP3  
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