CS8900A
Crystal LAN™ ISA Ethernet Controller
4.4.6 Register 3: Receiver Configuration
(RxCFG, Read/Write, Address: PacketPage base + 0102h)
7
6
5
4
3
2
1
9
0
StreamE
Skip_1
000011
F
E
D
C
B
A
8
ExtradataiE
RuntiE
CRCerroriE
BufferCRC AutoRx DMAE RxDMA only
RxOKiE
RxCFG determines how frames will be transferred to the host and what frame types will cause interrupts.
000011
These bits provide an internal address used by the CS8900A to identify this as the Reveiver
Configuration Register.
Skip_1
When set, this bit causes the last committed received frame to be deleted from the receive buff-
er. To skip another frame, the host must rewrite a “1” to this bit. This bit is not to be used if
RxDMAonly (Bit 9) is set. Skip_1 is an Act-Once bit. See Section 5.2.5 on page 84.
StreamE
RxOKiE
When set, StreamTransfer mode is used to transfer receive frames that are back-to-back and
that pass the Destination Address filter (see Section 5.3 on page 87). When StreamE is clear,
StreamTransfer mode is not used. This bit must not be set unless either bit AutoRxDMA or bit
RXDMAonly is set.
When set, there is an RxOK Interrupt if a frame is received without errors. RxOK interrupt is
not generated when DMA mode is used for frame reception.
RxDMAonly
The Receive-DMA mode is used for all receive frames when this bit is set.
AutoRxDMAE
When set, the CS8900A will automatically switch to Receive-DMA mode if the conditions spec-
ified in Section 5.5 on page 93 are met. RxDMAonly (Bit 9) has precedence over AutoRxD-
MAE.
BufferCRC
When set, the received CRC is included with the data stored in the receive-frame buffer, and
the four CRC bytes are included in the receive-frame length (PacketPage base + 0402h). When
clear, neither the receive buffer nor the receive length include the CRC.
CRCerroriE
RuntiE
When set, there is a CRCerror Interrupt if a frame is received with a bad CRC.
When set, ther is a Runt Interrupt if a frame is received that is shorter than 64 bytes. The
CS8900A always discards any frame that is shorter than 8 bytes.
ExtradataiE
When set, there is an Extradata Interrupt if a frame is received that is longer than 1518 bytes.
The operation of this bit is independent of the received packet integrity (good or bad CRC).
After reset, if no EEPROM is found by the CS8900A, then the register has the following initial state. If an EEPROM
is found, then the register’s initial value may be set by the EEPROM. See Section 3.3 on page 19.
Reset value is: 0000 0000 0000 0011
CIRRUS LOGIC PRODUCT DATA SHEET
DS271PP3
53
CIRRUS [ CIRRUS LOGIC ]
