CS8900A
Crystal LAN™ ISA Ethernet Controller
4.4.13 Register C: Buffer Event
(BufEvent, Read-only, Address: PacketPage base + 012Ch)
7
6
5
4
3
2
1
0
RxDMA frame
SWint
001100
F
E
D
C
B
A
9
8
RxDest
Rx128
RxMiss
TxUnder run
Rdy4Tx
BufEvent gives the status of the transmit and receive buffers.
001100
These bits provide an internal address used by the CS8900A to identify this as the Buffer Event
Register. When reading this register, these bits will be 001100, where the LSB corresponds to
Bit 0.
SWint
If set, there has been a software initiated interrupt. This bit is used in conjunction with the SWint-
X bit (Register B, BufCFG, Bit 6).
RxDMAFrame
Rdy4Tx
If set, one or more received frames have been transferred by slave DMA. If RxDMAiE (Register
B, BufCFG, Bit 7) is set, there is an interrupt.
If set, the CS8900A is ready to accept a frame from the host for transmission. If Rdy4TxiE (Reg-
ister B, BufCFG, Bit 8) is set, there is an interrupt. (See Section 5.7 on page 99 for a description
of the transmit bid process.)
TxUnderrun
RxMiss
This bit is set if CS8900A runs out of data before it reaches the end of the frame (called a trans-
mit underrun). If TxUnderruniE (Register B, BufCFG, Bit 9) is set, there is an interrupt.
If set, one or more receive frames have been lost due to slow movement of data out of the re-
ceive buffers. If RxMissiE (Register B, BufCFG, Bit A) is set, there is an interrupt.
Rx128
This bit is set after the first 128 bytes of an incoming frame have been received. This bit will
allow the host the option of preprocessing frame data before the entire frame is received. If
Rx128iE (Register B, BufCFG, Bit B) is set, there is an interrupt.
RxDest
When set, this bit shows that a receive frame has passed the Destination Address Filter criteria
as defined in the RxCTL register (Register 5). This bit is useful as an early indication of an in-
coming frame. It will be earlier than Rx128 (Register C, BufEvent, Bit B). If RxDestiE (Register
B, BufCFG, Bit F) is set, there is an interrupt.
Reset value is: 0000 0000 0000 1100
Notes: With any event register, like BufEvent, all bits are cleared upon readout. The host is responsible for
processing all event bits.
CIRRUS LOGIC PRODUCT DATA SHEET
60
DS271PP3
CIRRUS [ CIRRUS LOGIC ]
