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CS8900A-IQ3 参数 Datasheet PDF下载

CS8900A-IQ3图片预览
型号: CS8900A-IQ3
PDF下载: 下载PDF文件 查看货源
内容描述: 水晶局域网? ISA以太网控制器 [Crystal LAN ⑩ ISA Ethernet Controller]
分类和应用: 控制器局域网以太网
文件页数/大小: 128 页 / 1360 K
品牌: CIRRUS [ CIRRUS LOGIC ]
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CS8900A  
Crystal LAN™ ISA Ethernet Controller  
event occurs, but then does not accept the receive  
frame (the length of the receive frame is set to ze-  
ro).  
Interrupt Enable Bit  
(register name)  
Event Bit or Counter  
(register name)  
ExtradataiE (RxCFG)  
RuntiE (RxCFG)  
Extradata (RxEvent)  
Runt (RxEvent)  
The other five Accept bits in RxCTL are used for  
destination address filtering (see Section 5.3 on  
page 87). The Accept mechanism is explained in  
more detail in Section 5.2 on page 79.  
CRCerroriE (RxCFG)  
RxOKiE (RxCFG)  
CRCerror (RxEvent)  
RxOK (RxEvent)  
16colliE (TxCFG)  
AnycolliE (TxCFG)  
16coll (TxEvent)  
4.4.4 Status and Control Register Summary  
“Number-of Tx-collisions”  
counter is incremented  
(TxEvent)  
The table on the following page (Table 15) pro-  
vides a summary of the Status and Control regis-  
ters. Section 4.4.4 on page 49 gives a detailed  
description of each Status and Control register.  
JabberiE (TxCFG)  
Jabber (TxEvent)  
Out-of-windowiE (TxCFG) Out-of-window (TxEvent)  
TxOKiE (TxCFG)  
SQEerroriE (TxCFG)  
Loss-of-CRSiE (TxCFG)  
TxOK (TXEvent)  
SQEerror (TxEvent)  
Loss-of-CRS (TxEvent)  
MissOvfloiE (BufCFG)  
RxMISS counter over-  
flows past 1FFh  
TxColOvfloiE (BufCFG) TxCOL counter overflows  
past 1FFh  
RxDestiE (BufCFG)  
Rx128iE (BufCFG)  
RxDest (BufEvent)  
Rx128 (BufEvent)  
RxMissiE (BufCFG)  
TxUnderruniE (BufCFG)  
Rdy4TxiE (BufCFG)  
RxDMAiE (BufCFG)  
RxMISS (BufEvent)  
TxUnderrun (BufEvent)  
Rdy4Tx (BufEvent)  
RxDMAFrame (BufEvent)  
Table 14. Interrupt Enable Bits and Events  
operations. It is possible to set either, neither, or  
both bits. The four corresponding pairs of bits are:  
IE Bit in RxCFG  
ExtradataiE  
RuntiE  
A Bit in RxCTL  
ExtradataA  
RuntA  
CRCerroriE  
RxOKiE  
CRCerrorA  
RxOKA  
If one of the above Interrupt Enable bits is set and  
the corresponding Accept bit is clear, the CS8900A  
generates an interrupt when the associated receive  
CIRRUS LOGIC PRODUCT DATA SHEET  
DS271PP3  
49  
 
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