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CS5508-BS 参数 Datasheet PDF下载

CS5508-BS图片预览
型号: CS5508-BS
PDF下载: 下载PDF文件 查看货源
内容描述: 非常低功耗的16位和20位A / D转换器 [VERY LOW POWER 16BIT AND 20 BIT A/D CONVERTERS]
分类和应用: 转换器
文件页数/大小: 40 页 / 722 K
品牌: CIRRUS [ CIRRUS LOGIC ]
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CS5505/6/7/8  
If the CS5505/6/7/8 is operated at a clock rate  
other than 32.768 kHz, the filter characteristics,  
including the comb filter zeros, will scale with  
the operating clock frequency. Therefore, opti-  
mum rejection of line frequency interference will  
occur with the CS5505/6/7/8 running at  
32.768 kHz. The CS5505/6/7/8 can be used with  
external clock rates from 30 kHz to 163 kHz.  
ponents should be removed by means of low-  
pass filtering prior to the A/D input to prevent  
aliasing. Spectral components greater than one  
half the output word rate on the VREF inputs  
(VREF+ and VREF-) may also be aliased. Fil-  
tering of the reference voltage to remove these  
spectral components from the reference voltage  
is desirable.  
Anti-Alias Considerations for Spectral  
Measurement Applications  
Crystal Oscillator  
The CS5505/6/7/8 is designed to be operated us-  
ing a 32.768 kHz "tuning fork" type crystal. One  
end of the crystal should be connected to the  
XIN input. The other end should be attached to  
XOUT. Short lead lengths should be used to  
minimize stray capacitance. Figure 12 illustrates  
the gate oscillator, and a simplified version of  
the control logic used on the chip.  
Input frequencies greater than one half the out-  
put word rate (CONV = 1) may be aliased by  
the converter. To prevent this, input signals  
should be limited in frequency to no greater than  
one half the output word rate of the converter  
(when CONV =1). Frequencies close to the  
modulator sample rate (XIN/2) and multiples  
thereof may also be aliased. If the signal source  
includes spectral components above one half the  
output word rate (when CONV = 1) these com-  
Over the industrial temperature range (-40 to  
+85 °C) the on-chip gate oscillator will oscillate  
CS5505/6  
Channel A0 A1  
D
Q
A0  
1
2
3
4
0
0
1
1
0
1
0
1
CLK  
Input  
Mux  
Decoder  
D
Q
A1  
CLK  
Start  
Conversion  
CONV  
S
Q
D
Q
CLK  
R
S
R
Start  
Calibration  
Q
Q
D
Q
CAL  
CLK  
R
T
10 M  
Modulator  
Sample  
Clock  
15 pF  
gm 19 umho  
22.5 pF  
~
~
XOUT  
XIN  
XTL=32.768 kHz  
Figure 12. Gate Oscillator and Control Logic  
20
DS59F5
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