CS5505/6/7/8
CS5505/6/7/8
Analog Input Impedance Considerations
V
occurs the instant the sample capacitor is
max
switched from the buffer output to the AIN pin.
Prior to switching, AIN has an error estimated as
The analog input of the CS5505/6/7/8 can be
modeled as illustrated in Figure 8 (the model ig-
nores the multiplexer switch resistance).
Capacitors (15 pF each) are used to dynamically
sample each of the inputs (AIN+ and AIN-).
Every half XIN cycle the switch alternately con-
nects the capacitor to the output of the buffer
and then directly to the AIN pin. Whenever the
sample capacitor is switched from the output of
the buffer to the AIN pin, a small packet of
charge (a dynamic demand of current) is re-
quired from the input source to settle the voltage
of the sample capacitor to its final value. The
voltage on the output of the buffer may differ up
to 100 mV from the actual input voltage due to
the offset voltage of the buffer. Timing allows
one half of a XIN clock cycle for the voltage on
the sample capacitor to settle to its final value.
The equation which defines the settling time is:
being less than or equal to V . V
is equal to
the prior error (V ) plus the additional error
e
max
e
from the buffer offset. The estimate for V
is:
max
15pF
(15pF + CEXT
V
max
= V + 100mV
e
)
Where C
or stray capacitance.
is the combination of any external
EXT
From the settling time equation, an equation for
the maximum acceptable source resistance is de-
rived.
−1
Rs
=
max
V
e
2XIN (15pF + C
) ln
EXT
15pF(100mv)
V +
e
(15pF + C
)
EXT
V = Vmax e−t
⁄
RC
e
This equation assumes that the offset voltage of
the buffer is 100 mV, which is the worst case.
The value of Ve is the maximum error voltage
which is acceptable.
Where Ve is the final settled value, V
max
is the
maximum error voltage value of the input signal,
R is the value of the input source resistance, C is
the 15 pF sample capacitor plus the value of any
stray or additional capacitance at the input pin.
The value of t is equal to 1/(2XIN).
For a maximum error voltage (Ve) of 10 µV in
the CS5505 (1/4LSB at 16-bits) and 600 nV in
the CS5506 (1/4LSB at 20-bits), the above equa-
tion indicates that when operating from a
32.768 kHz XIN, source resistances up to
110 kΩ in the CS5505 or 84 kΩ in the CS5506
are acceptable in the absence of external capaci-
CS5505/6/7/8
AIN+
15 pF
+
V
V
< 100 mV
< 100 mV
os
os
Internal
Bias
Voltage
tance (C
= 0). If higher input source
-
EXT
resistances are desired the master clock rate can
be reduced to yield a longer settling time.
AIN-
15 pF
+
-
The VREF+ and VREF- inputs have nearly the
same structure as the AIN+ and AIN- inputs.
Therefore, the discussion on analog input imped-
ance applies to the voltage reference inputs as
well.
Figure 8. Analog Input Model
1188
DDSS5599FF54
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