CS5505/6/7/8
CS5505/6/7/8
analog ground pin. No analog ground pin is re-
quired because the inputs for measurement and
for the voltage reference are differential and re-
quire no ground. In the digital section of the
chip the supply current flows into the VD+ pin
and out of the DGND pin. As a CMOS device,
the CS5505/6/7/8 requires that the supply volt-
age on the VA+ pin always be more positive
than the voltage on any other pin of the device.
If this requirement is not met, the device can
latch-up or be damaged. In all circumstances the
VA+ voltage must remain more positive than the
VD+ or DGND pins; VD+ must remain more
positive than the DGND pin.
The following power supply options are possi-
ble:
VA+ = +5V to +10V, VA- = 0V,
VD+ = +5V
VD+ = +5V
VA+ = +5V,
VA+ = +5V,
VA- = -5V,
VA- = 0V to -5V, VD+ = +3.3V
The CS5505/6/7/8 cannot be operated with a
3.3V digital supply if VA+ is greater than
+5.5V.
10Ω
+5V
Analog
Supply
0.1
0.1
µ
F
µ
F
17
20
VA+
VD+
Optional
Clock
Source
5
6
XIN
4
8
Calibration
Control
CAL
XOUT
M/SLP
32.768 kHz
Bipolar/
Unipolar
Input Select
7
Sleep Mode
BP/UP
CS5505/6
AIN1+
AIN2+
AIN3+
AIN4+
Control
and
Output Mode
Select
9
10
12
13
Analog*
Signal
Sources
21
22
Serial
Data
Interface
SCLK
SDATA
11
Signal
Ground
AIN-
23
2
1
*Unused analog inputs
should be tied to AIN-
DRDY
CS
14
Control
Logic
+
VREF+
A0
A1
Voltage
Reference
24
15
16
3
-
VREF-
CONV
DGND
19
VREFOUT
Unused Logic
inputs must be
connected to
VA-
18
VD+ or DGND.
Note: To use the internal 2.5 volt reference see Figure 6.
Figure 14. CS5505/6 System Connection Diagram Using External Reference, Single Supply
DDSS599FF45
2233