CS5463
ANALOG CHARACTERISTICS (Continued)
Parameter
Analog Inputs (Voltage Channel)
Symbol
Min
Typ
Max
Unit
mV
Differential Input Range
Total Harmonic Distortion
[(VIN+) - (VIN-)]
VIN
-
500
-
P-P
THD
65
-
75
-70
0.2
-
-
dB
dB
Crosstalk with Current Channel at Full Scale (50, 60 Hz)
-
Input Capacitance
All Gain Ranges
IC
-
-
-
pF
Effective Input Impedance
Noise (Referred to Input)
EII
2
-
MΩ
N
-
140
µV
V
rms
Offset Drift (Without the High Pass Filter)
Gain Error
OD
GE
-
-
16.0
±3.0
-
µV/°C
%
(Note 3)
Temperature Channel
Temperature Accuracy
Power Supplies
T
-
±5
-
°C
Power Supply Currents (Active State)
I
PSCA
PSCD
PSCD
-
-
-
1.3
2.9
1.7
-
-
-
mA
mA
mA
A+
I
(VA+ = VD+ = 5 V)
D+
I
(VA+ = 5 V, VD+ = 3.3 V)
D+
Power Consumption
(Note 4)
Active State (VA+ = VD+ = 5 V)
Active State (VA+ = 5 V, VD+ = 3.3 V)
Stand-by State
PC
-
-
-
-
21
11.6
8
29
17.5
-
-
mW
mW
mW
µW
Sleep State
10
Power Supply Rejection Ratio
(Note 5)
(50, 60 Hz)
Voltage Channel
Current Channel
-
65
75
-
-
-
PSRR
45
70
dB
dB
PFMON Low-voltage Trigger Threshold
PFMON High-voltage Power-on Trip Point
(Note 6) PMLO
(Note 7) PMHI
2.3
-
2.45
2.55
-
V
V
2.7
Notes: 3. Applies before system calibration.
4. All outputs unloaded. All inputs CMOS level.
5. Definition for PSRR: VREFIN tied to VREFOUT, VA+ = VD+ = 5 V, a 150 mV (zero-to-peak) (60 Hz)
sinewave is imposed onto the +5 V DC supply voltage at VA+ and VD+ pins. The “+” and “-” input pins
of both input channels are shorted to AGND. Then the CS5463 is commanded to continuous conversion
acquisition mode, and digital output data is collected for the channel under test. The (zero-to-peak)
value of the digital sinusoidal output signal is determined, and this value is converted into the
(zero-to-peak) value of the sinusoidal voltage (measured in mV) that would need to be applied at the
channel’s inputs, in order to cause the same digital sinusoidal output. This voltage is then defined as
Veq. PSRR is then (in dB):
150
Veq
---------
PSRR = 20 ⋅ log
6. When voltage level on PFMON is sagging, and LSD bit is at 0, the voltage at which LSD bit is set to 1.
7. If the LSD bit has been set to 1 (because PFMON voltage fell below PMLO), this is the voltage level on
PFMON at which the LSD bit can be permanently reset back to 0.
8
DS678PP1
CIRRUS [ CIRRUS LOGIC ]
