CS5101A CS5102A
Digital Outputs
STBY - Standby (Calibrating), PIN 5.
Indicates calibration status after reset. Remains low throughout the calibration sequence and
returns high upon completion.
SDATA - Serial Output, PIN 15.
Presents each output data bit on a falling edge of SCLK. Data is valid to be latched on the
rising edge of SCLK.
SSH/SDL - Simultaneous Sample/Hold / Serial Data Latch, PIN 11.
Used to control an external sample/hold amplifier to achieve simultaneous sampling between
channels. In FRN and SSC modes (SCLK is an output), this signal provides a convenient latch
signal which forms the 16 data bits. This can be used to control external serial to parallel
latches, or to control the serial port in a DSP.
TRK1, TRK2 - Tracking Channel 1, Tracking Channel 2, PINS 8 and 9.
Falls low at the end of a conversion cycle, indicating the acquisition phase for the
corresponding channel. The TRK1 or TRK2 pin will return high at the beginning of conversion
for that channel.
Analog Outputs
REFBUF - Reference Buffer Output, PIN 21.
Reference buffer output. A 0.1 µF ceramic capacitor must be tied between this pin and VA-.
Miscellaneous
TEST - Test, PIN 26.
Allows access to the CS5101A’s and the CS5102A’s test functions which are reserved for
factory use. Must be tied to VD+.
34
DS45F2
CIRRUS [ CIRRUS LOGIC ]
