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CS5101A-JL16 参数 Datasheet PDF下载

CS5101A-JL16图片预览
型号: CS5101A-JL16
PDF下载: 下载PDF文件 查看货源
内容描述: 16位, 100kHz的/ 20kHz的A / D转换器 [16-Bit, 100kHz/ 20kHz A/D Converters]
分类和应用: 转换器
文件页数/大小: 40 页 / 461 K
品牌: CIRRUS [ CIRRUS LOGIC ]
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CS5101A CS5102A  
Power Supply Connections  
VD+ - Positive Digital Power, PIN 7.  
Positive digital power supply. Nominally +5 volts.  
VD- - Negative Digital Power, PIN 1.  
Negative digital power supply. Nominally -5 volts.  
DGND - Digital Ground, PIN 6.  
Digital ground [reference].  
VA+ - Positive Analog Power, PIN 25.  
Positive analog power supply. Nominally +5 volts.  
VA- - Negative Analog Power, PIN 23.  
Negative analog power supply. Nominally -5 volts.  
AGND - Analog Ground, PIN 22.  
Analog ground reference.  
Oscillator  
CLKIN - Clock Input, PIN 3.  
All conversions and calibrations are timed from a master clock which can be externally  
supplied by driving CLKIN [this input TTL-compatible, CMOS recommended].  
XOUT - Crystal Output, PIN 4.  
The master clock can be generated by tying a crystal across the CLKIN and XOUT pins. If an  
external clock is used, XOUT must be left floating.  
Digital Inputs  
HOLD - Hold, PIN 12.  
A falling transition on this pin sets the CS5101A or CS5102A to the hold state and initiates a  
conversion. This input must remain low for at least 1/tclk + 20 ns. When operating in Free Run  
Mode, HOLD is disabled, and should be tied to DGND or VD+.  
CRS/FIN - Coarse Charge/Fine Charge Control, PIN 10.  
When brought high during acquisition time, CRS/FIN forces the CS5101A or CS5102A into  
coarse charge state. This engages the internal buffer amplifier to track the analog input and  
charges the capacitor array much faster, thereby allowing the CS5101A or CS5102A to track  
high slewing signals. In order to get an accurate sample, the last coarse charge period before  
initiating a conversion (bringing HOLD low) must be longer than 0.75 µs (CS5101A) or  
3.75 µs (CS5102A). Similarly, the fine charge period immediately prior to conversion must be  
at least 1.125 µs (CS5101A) or 5.625 µs (CS5102A). The CRS/FIN pin must be low during  
conversion time. For normal operation, CRS/FIN should be tied low, in which case the  
CS5101A or CS5102A will automatically enter coarse charge for 6 clock cycles immediately  
after the end of conversion.  
32  
DS45F2  
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