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CS5101A-JL16 参数 Datasheet PDF下载

CS5101A-JL16图片预览
型号: CS5101A-JL16
PDF下载: 下载PDF文件 查看货源
内容描述: 16位, 100kHz的/ 20kHz的A / D转换器 [16-Bit, 100kHz/ 20kHz A/D Converters]
分类和应用: 转换器
文件页数/大小: 40 页 / 461 K
品牌: CIRRUS [ CIRRUS LOGIC ]
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CS5101A CS5102A  
CH1/2 - Left/Right Input Channel Select, PIN 13.  
Status at the end of a conversion cycle determines which analog input channel will be acquired  
for the next conversion cycle. When in Free Run Mode, CH1/2 is an output, and will indicate  
which channel is being sampled during the current acquisition phase.  
SLEEP - Sleep, PIN 28.  
When brought low causes the CS5101A or CS5102A to enter a power-down state. All  
calibration coefficients are retained in memory, so no recalibration is needed after returning to  
the normal operating mode. If using the internal crystal oscillator, time must be allowed after  
SLEEP returns high for the crystal oscillator to stabilize. SLEEP should be tied high for normal  
operation.  
CODE - 2’s Complement/Binary Coding Select, PIN 16.  
Determines whether output data appears in 2’s complement or binary format. If high, 2’s  
complement; if low, binary.  
BP/UP - Bipolar/Unipolar Input Range Select, PIN 17.  
When low, the CS5101A or CS5102A accepts a unipolar input range from AGND to VREF.  
When high, the CS5101A or CS5102A accepts bipolar inputs from -VREF to +VREF.  
SCKMOD - Serial Clock Mode Select, PIN 27.  
When high, the SCLK pin is an input; when low, it is an output. Used in conjunction with  
OUTMOD to select one of 4 output modes described in Table 2.  
OUTMOD - Output Mode Select, PIN 18.  
The status of SCKMOD and OUTMOD determine which of four output modes is utilized. The  
four modes are described in Table 2.  
SCLK - Serial Clock, PIN 14.  
Serial data changes status on a falling edge of this input, and is valid on a rising edge. When  
SCKMOD is high SCLK acts as an input. When SCKMOD is low the CS5101A or CS5102A  
generates its own serial clock at one-fourth the master clock frequency and SCLK is an output.  
RST - Reset, PIN 2.  
When taken low, all internal digital logic is reset. Upon returning high, a full calibration  
sequence is initiated which takes 11,528,160 CLKIN cycles (CS5101A) or 2,882,040 CLKIN  
cycles (CS5102A) to complete. During calibration, the HOLD input will be ignored. The  
CS5101A or CS5102A must be reset at power-up for calibration, however; calibration is  
maintained during SLEEP mode, and need not be repeated when resuming normal operation.  
Analog Inputs  
AIN1, AIN2 - Channel 1 and 2 Analog Inputs, PINS 19 and 24.  
Analog input connections for the left and right input channels.  
VREF - Voltage Reference, PIN 20.  
The analog reference voltage which sets the analog input range. In unipolar mode VREF sets  
full-scale; in bipolar mode its magnitude sets both positive and negative full-scale.  
DS45F2  
33  
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