CS5012A, CS5014, CS5016
HOLD
CS
X
CAL
X
INTRLV
RD
X
A0
*
RST
Function
Hold and Start Convert
X
X
X
0
0
0
0
0
Initiate Burst Calibration
X
1
0
1
X
*
Stop Burst Cal and Begin Track
0
0
X
*
Initiate Interleave Calibration
Terminate Interleave Cal
Read Output Data
X
0
X
X
*
X
X
1
0
0
0
1
X
X
X
X
1
X
X
X
X
0
0
X
*
1
0
*
0
0
0
X
Read Status Register
X
High Impedance Data Bus
X
X
0
X
X
0
X
X
X
X
X
X
1
X
X
*
X
0
X
1
High Impedance Data Bus
Reset
Reset
X
*
The status of A0 is not critical to the operation specified. However, A0 should not be low with
CS and HOLD low, or a software reset will result.
Table 4. CS5012A/14/16 Truth Table
+5V
Analog
Supply
10
Ω
25
11
0.1 µF
VA+
VD+
BW
0.1 µF
33
24
Mode
Select *
BP/UP
Clock
Source
(optional)
20
CLKIN
CS5012A
CS5014
CS5016
Serial
Data
Interface
40
39
SDATA
SCLK
(optional)
Analog
Signal
Source
200
Ω
Data
Signal
Conditioning
26
AIN
8 or 16
38
D0-D15
Processor
1000 pF
EOC
EOT
May be
microprocessor
or discrete logic.
37
1
HOLD
35
0
VREF
or
CAL
INTRLV
CS
Control
Logic
34
21
22
23
32
31
10
±VREF
RD
28
Voltage
VREF
AGND
A0
Reference
0.01
µ
F
Unused Logic inputs should only
be connected to VD+ or DGND.
RESET
Reset
Generator
10
µ
F
27
29
* BW and BP/UP should always
be terminated to VD+ or DGND,
or driven by a logic gate.
TST
REFBUF
VA-
DGND
0.1 µF
0.1
µ
F
VD- 0.1
µF
For best dynamic
S/(N+D) performance.
30
36
-5V
10
Ω
Analog
Supply
Figure 36. CS5012A/14/16 System Connection Diagram
DS14F6
2-39
CIRRUS [ CIRRUS LOGIC ]
