CS5012A, CS5014, CS5016
0dB
-20dB
-40dB
-60dB
-80dB
-100dB
-120dB
0dB
-20dB
-40dB
-60dB
-80dB
-100dB
-120dB
Sampling Rate: 56 kHz
Full Scale: 9V p-p
S/(N+D): 81.5 dB
Sampling Rate: 56 kHz
Full Scale: 9V p-p
S/(N+D): 64.6 dB
Signal
Signal
Amplitude
Relative to
Full Scale
Amplitude
Relative to
Full Scale
12 kHz
28 kHz
12 kHz
28 kHz
dc
dc
Input Frequency
Input Frequency
Figure 31. CS5014 FFT plot with 12 kHz
Full Scale Input
Figure 32. CS5014 FFT plot with 12 kHz
-20 dB Input
0dB
0dB
Sampling Rate: 50 kHz
Sampling Rate: 50 kHz
Full Scale: 9V p-p
S/(N+D): 71.9 dB
-20dB
-40dB
Full Scale: 9V p-p
S/(N+D): 84.3 dB
-20dB
-40dB
-60dB
Signal
-60dB
Signal
Amplitude
Relative to
Full Scale
Amplitude
Relative to
Full Scale
-80dB
-80dB
-100dB
-120dB
-100dB
-120dB
12 kHz
Input Frequency
25 kHz
12 kHz
Input Frequency
25 kHz
dc
dc
Figure 34. CS5016 FFT plot with 12 kHz
-20 dB Input
Figure 33. CS5016 FFT plot with 12 kHz
Full Scale Input
Clock Feedthrough in the CS5014 and CS5016
(Figure 35), but the probability of this occurring
is small since the peaks are spikes of short dura-
tion.
Maintaining the integrity of analog signals in the
presence of digital switching noise is a difficult
problem. The CS5014/16 can be synchronized to
the digital system using the CLKIN input to
avoid conversion errors due to asynchronous in-
terference. However, digital interference will still
affect sampling purity due to coupling between
the CS5014/16’s analog input and master clock.
Master Clock
Analog Input
Clock Feedthrough
Int/Ext Freq Source Impedance RMS Peak-to-Peak
Internal 2MHz
External 2MHz
External 4MHz
External 4MHz
External 4MHz
50
50
15uV
25uV
40uV
25uV
80uV
70uV
110uV
150uV
110uV
325uV
50
25
200
The effect of clock feedthrough depends on the
sampling conditions. If the sampling signal at the
HOLD input is synchronized to the master clock,
clock feedthrough will appear as a dc offset at the
CS5014/16’s output. The offset could theoreti-
cally reach the peak coupling magnitude
Figure 35. Examples of Measured Clock Feedthrough
If sampling is performed asynchronously with the
master clock, clock feedthrough will appear as an
ac error at the CS5014/16’s output. With a fixed
2-36
DS14F6
CIRRUS [ CIRRUS LOGIC ]
