CS5012A, CS5014, CS5016
VREF – Voltage Reference, PIN 28.
The analog reference voltage which sets the analog input range. It represents positive full scale for
both bipolar and unipolar operation, and its magnitude sets negative full scale in bipolar mode.
Digital Outputs
D0 through D15 – Data Bus Outputs, PINS 2 thru 9, 12 thru 19.
3-state output pins. Enabled by CS and RD, they offer the converter’s output in a format
consistent with the state of BW if A0 is high. If A0 is low, bits D0-D7 offer status register data.
EOT – End Of Track, PIN 37.
If low, indicates that enough time has elapsed since the last conversion for the device to acquire
the analog input signal.
EOC – End Of Conversion, PIN 38.
This output indicates the end of a conversion or calibration cycle. It is high during a conversion
and will fall to a low state upon completion of the conversion cycle indicating valid data is
available at the output. Returns high on the first subsequent read or the start of a new conversion
cycle.
SDATA – Serial Output, PIN 40.
Presents each output data bit after it is determined by the successive approximation algorithm.
Valid on the rising edge of SCLK, data appears MSB first, LSB last, and each bit remains valid
until the next bit appears.
SCLK – Serial Clock Output, PIN 39.
Used to clock converted output data serially from the CS5012A/14/16. Serial data is stable on the
rising edge of SCLK.
Analog Outputs
REFBUF – Reference Buffer Output, PIN 29.
Reference buffer output. A 0.1 µF ceramic capacitor must be tied between this pin and VA-.
Miscellaneous
TST – Test, PIN 31.
Allows access to the CS5012A/14/16’s test functions which are reserved for factory use. Must be
tied to DGND.
DS14F6
2-43
CIRRUS [ CIRRUS LOGIC ]
