CS5012A, CS5014, CS5016
Count
5000
formed on the charge trapped on the capacitor ar-
ray at the moment the HOLD command is given.
The charge on the array is ideally related to the
analog input voltage by Q = -V x C as
Noiseless
Converter
CS5016
4000
in
in
tot
shown in Figure 2. Any deviation from this ideal
relationship will result in conversion errors even
if the conversion process proceeds flawlessly.
3000
2000
At dc, the DAC capacitor array’s voltage coeffi-
cient dictates the converter’s linearity. This
variation in capacitance with respect to applied
signal voltage yields a nonlinear relationship be-
1000
tween charge Q and the analog input voltage
80CA 80CB 80CC 80CD 80CE 80CF
Code (Hexadecimal)
80D0
0
in
V
in
and places a bow or wave in the transfer
Counts:
0
11
911
3470
599
9
function. This is the dominant source of distor-
tion at low input frequencies (Figures 22 and 24).
Figure 30. Histogram Plot of 5000 Conversion
Inputs from the CS5016
The ideal relationship between Q and V can
in
in
are therefore used to remove frequency compo-
nents in the input signal which are above one-half
the sample rate. However, all wideband noise in-
troduced by the CS5016 still aliases into the
baseband. This "white" noise is evenly spread
from dc to one-half the sampling rate and inte-
grates to 35 µV rms in unipolar mode.
also be distorted at high signal frequencies due to
nonlinearities in the internal MOS switches. Dy-
namic signals cause ac current to flow through
the switches connecting the capacitor array to the
analog input pin in the track mode. Nonlinear on-
resistance in the switches causes a nonlinear
voltage drop. This effect worsens with increased
signal frequency as shown in Figures 26 and 28
since the magnitude of the steady state current in-
creases. First noticeable at 1 kHz, this distortion
assumes a linear relationship with input fre-
quency. With signals 20 dB or more below
full-scale, it no longer dominates the converter’s
overall S/(N+D) performance (Figures 31-34).
Noise can be reduced by sampling at higher than
the desired word rate and averaging multiple
samples for each word. Oversampling spreads the
CS5016’s noise over a wider band (for lower
noise density), and averaging applies a low-pass
response which filters noise above the desired
signal bandwidth. In general, the CS5016’s noise
performance can be maximized in any application
by always sampling at the maximum specified
rate of 50 kHz (for lowest noise density) and
digitally filtering to the desired signal bandwidth.
This distortion is strictly an ac sampling phe-
nomenon. If significant energy exists at high
frequencies, the effect can be eliminated using an
external track-and-hold amplifier to allow the ar-
ray’s charge current to decay, thereby eliminating
any voltage drop across the switches. Since the
CS5014/16 has a second sampling function on-
chip, the external track-and-hold can return to the
track mode once the converter’s HOLD input
falls. It need only acquire the analog input by the
time the entire conversion cycle finishes.
CS5014 and CS5016 Sampling Distortion
The ultimate limitation on the CS5014/16’s
linearity (and distortion) arises from nonideal
sampling of the analog input voltage. The cali-
brated capacitor array used during conversions is
also used to track and hold the analog input sig-
nal. The conversion is not performed on the
analog input voltage per se, but is actually per-
DS14F6
2-35
CIRRUS [ CIRRUS LOGIC ]
