CS5012A, CS5014, CS5016
1 / Throughput
HOLD
Input
1 / Throughput
(64 + N cycles)
HOLD
Input
Conversion
(49 + N cycles)
Conversion
*
EOC
Output
EOC
Output
Acquisition
(15 cycles)
Acquisition
EOT
EOT
Output
Output
*Dashed line: CS & RD = 0 CS5012A N = 0
Solid line: See Figure 9
Synchronization Uncertainty (4 cycles)
CS5014 N = 8
CS5016 N = 16
Figure 5b. Synchronous (Loopback Mode)
Figure 5a. Asynchronous Sampling (External Clock)
Asynchronous Sampling
Synchronous Sampling
The CS5012A/14/16 internally operate from a
clock which is delayed and divided down from
To achieve maximum throughput, sampling can
be synchronized with the internal conversion
clock by connecting the End-of-Track (EOT) out-
put to HOLD (Figure 3b). The EOT output falls
15 CLKIN cycles after EOC indicating the ana-
log input has been acquired to the
CS5012A/14/16’s specified accuracy. The EOT
output is synchronized to the internal conversion
clock, so the four clock cycle synchronization un-
certainty is removed yielding throughput at
CLKIN (f
/4). If sampling is not synchronized
CLK
to this internal clock, the conversion cycle may
not begin until up to four clock cycles after
HOLD goes low even though the charge is
trapped immediately. In this asynchronous mode
(Figure 3a), the four clock cycles add to the mini-
mum 49, 57 and 65 clock cycles (for the
CS5012A/14/16 respectively) to define the maxi-
mum conversion time (see Figure 5a and
Table 1).
[1/64]f
for the CS5012A, [1/72]f
for
CLK
CLK
CS5014 and [1/80]f
for CS5016 where f
CLK
CLK
is the CLKIN frequency (see Figure 5b and Ta-
ble 1).
Conversion Time
Throughput Time
Sampling Mode
CS5012A
Min
Max
Min
Max
49 t
49 t
+
64 t
64 t
Synchronous (Loopback)
clk
clk
clk
clk
49 t
49 t
53 t
53 t
235 ns
235 ns
N/A
N/A
59 t
59 t
-7
+
+
1.32
2.25
µ
s
clk
clk
clk
clk
clk
Asynchronous
+
-12,-24
µ
s
clk
CS5014
57 t
57 t
57 t
+
72 t
N/A
72 t
Synchronous (Loopback)
Asynchronous
clk
clk
clk
clk
clk
clk
61 t
235 ns
67 t
+
clk
2.25
µ
µ
s
s
clk
CS5016
65 t
65 t
65 t
+
80 t
N/A
80 t
Synchronous (Loopback)
Asynchronous
clk
clk
clk
clk
69 t
235 ns
75 t
2.25
+
clk
clk
Table 1. Conversion and Throughput Times (t = Master Clock Period)
clk
2-20
DS14F6
CIRRUS [ CIRRUS LOGIC ]
