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CS49326 参数 Datasheet PDF下载

CS49326图片预览
型号: CS49326
PDF下载: 下载PDF文件 查看货源
内容描述: 多标准音频解码器系列 [Multi-Standard Audio Decoder Family]
分类和应用: 解码器
文件页数/大小: 86 页 / 1343 K
品牌: CIRRUS [ CIRRUS LOGIC ]
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CS49300 Family DSP  
SDATAN1—PCM Audio Data Input Number One: Pin 22  
Digital-audio data input that can accept from one to six channels of compressed or PCM data.  
SDATAN1 can be sampled with either edge of SCLKN1, depending on how SCLKN1 has been  
configured. INPUT  
CMPCLK, SCLKN2—PCM Audio Input Bit Clock: Pin 28  
Bidirectional digital-audio bit clock that is an output in master mode and an input in slave  
mode. In slave mode, SCLKN2 operates asynchronously from all other CS493XX clocks. In  
master mode, SCLKN2 is derived from the CS493XX internal clock generator. In either master  
or slave mode, the active edge of SCLKN2 can be programmed by the DSP. If the CDI is  
configured for bursty delivery, CMPCLK is an input used to sample CMPDAT.  
BIDIRECTIONAL - Default: INPUT  
CMPREQ, LRCLKN2—PCM Audio Input Sample Rate Clock: Pin 29  
When the CDI is configured as a digital audio input, this pin serves as a bidirectional digital-  
audio frame clock that is an output in master mode and an input in slave mode. LRCLKN2  
typically is run at the sampling frequency. In slave mode, LRCLKN2 operates asynchronously  
from all other CS493XX clocks. In master mode, LRCLKN2 is derived from the CS493XX  
internal clock generator. In either master or slave mode, the polarity of LRCLKN2 for a  
particular subframe can be programmed by the DSP. When the CDI is configured for bursty  
delivery, or parallel audio data delivery is being used, CMPREQ is an output which serves as  
an internal FIFO monitor. CMPREQ is an active low signal that indicates when another block  
of data can be accepted. BIDIRECTIONAL - Default: INPUT  
CMPDAT, SDATAN2—PCM Audio Data Input Number Two: Pin 27  
Digital-audio data input that can accept from one to six channels of compressed or PCM data.  
SDATAN2 can be sampled with either edge of SCLKN2, depending on how SCLKN2 has been  
configured. Similarly CMPDAT is the compressed data input pin when the CDI is configured  
for bursty delivery. When in this mode, the CS493XX internal PLL is driven by the clock  
recovered from the incoming data stream. INPUT  
DC—Reserved: Pin 38  
This pin is reserved and should be pulled up with an external 4.7k resistor.  
DD—Reserved: Pin 37  
This pin is reserved and should be pulled up with an external 4.7k resistor.  
84  
DS339PP4  
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