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CS49326 参数 Datasheet PDF下载

CS49326图片预览
型号: CS49326
PDF下载: 下载PDF文件 查看货源
内容描述: 多标准音频解码器系列 [Multi-Standard Audio Decoder Family]
分类和应用: 解码器
文件页数/大小: 86 页 / 1343 K
品牌: CIRRUS [ CIRRUS LOGIC ]
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CS49300 Family DSP  
byte, and the host should poll the Host Control  
Register again. If HINBSY is low, then the host  
byte response from the DSP. The host must read the  
response byte and act accordingly. The boot  
may write a control byte into the Host Message procedure is discussed in Section 8.1, “Host Boot”  
Register.  
on page 52.  
3) The host knows that the DSP is ready for a new  
During regular operation (at run-time), the  
control byte at this point and should write the responses from the CS493XX will always be 6  
control byte to the Host Message Register  
(A[1:0] = 00b).  
bytes in length.  
The example shown in this section can be used for  
any control read situation. The generic function  
‘Read_Byte_*()’ is used in the following example  
4) If the host would like to write any more control  
bytes to the CS493XX, the host should once  
again poll the Host Control Register (return to as  
a
generalized  
reference  
to  
either  
step 1).  
Read_Byte_MOT()  
or Read_Byte_INT().  
Figure 29 shows a typical read sequence. The  
protocol presented in Figure 29 will now be  
described in detail.  
6.2.3.2.Control Read in a Parallel Host Mode  
When reading control data from the CS493XX, the  
same protocol is used whether the host is reading a  
single byte or a 6 byte message.  
1) Optionally, INTREQ going low may be used as  
an interrupt to the host to indicate that the  
CS493XX has an outgoing message. Even with  
the use of INTREQ, HOUTRDY must be  
checked to insure that bytes are ready for the  
host during the read process. Please note that  
INTREQ does not go low to indicate an  
outgoing message during boot.  
During the boot procedure, a handshaking protocol  
is used by the CS493XX. This handshake consists  
of a 3 byte write to the CS493XX followed by a 1  
READ_BYTE_*(HOST CONTROL REGISTER)  
2) The host reads the Host Control Register  
(A[1:0] = 01b) in order to determine the state of  
the communication interface. Please note that  
‘Read_Byte_*()’ is a generalized reference to  
YES  
HINSBY==1  
either  
Read_Byte_MOT()  
or  
NO  
Read_Byte_INT().  
3) In order to determine whether the CS493XX  
has an outgoing control byte that is valid, the  
host must check the HOUTRDY bit of the Host  
Control Register (bit 1). If HOUTRDY is high,  
then the Host Message Register contains a valid  
message byte for the host. If HOUTRDY is  
low, then the DSP has not placed a new control  
byte in the Host Message Register, and the host  
should poll the Host Control Register again.  
WRITE_BYTE_*(HOST MESSAGE REGISTER)  
YES  
MORE BYTES  
TO WRITE?  
NO  
FINISHED  
4) The host knows that the DSP is ready to  
provide a new response byte at this point. The  
Figure 28. Typical Parallel Host Mode Control  
Write Sequence Flow Diagram  
DS339PP4  
47  
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