CS49300 Family DSP
When the host is downloading code to the
CS493XX or configuring the application code,
control messages will be written to (and read from)
the Host Message register. The Host Control
register is used during messaging sessions to
determine when the CS493XX can accept another
byte of control data, and when the CS493XX has an
outgoing byte that may be read.
•
•
Flow diagram and description for a control
write
Flow diagram and description for a control read
6.2.1. Intel Parallel Host Communication
Mode
The Intel parallel host communication mode is
implemented using the pins given in Table 6.
The PCM Data and Compressed Data registers are
used strictly for the transfer of audio data. The host
cannot read from these two registers. Audio data
written to registers 11b and 10b are transferred
directly to the internal FIFOs of the CS493XX.
When the level of the PCM FIFO reaches the FIFO
threshold level, the MFC bit of the Host Control
register will be set. When the level of the
Compressed Data FIFO reaches the FIFO threshold
level, the MFB bit of the Host Control register will
be set.
The INTREQ pin is controlled by the application
code when a parallel host communication mode has
been selected. When the code supports INTREQ
notification, the INTREQ pin is asserted whenever
the DSP has an outgoing message for the host. This
same information is reflected by the HOUTRDY
bit of the Host Control Register (A[1:0] = 01b).
INTREQ is useful for informing the host of
unsolicited messages. An unsolicited message is
defined as a message generated by the DSP without
an associated host read request. Unsolicited
messages can be used to notify the host of
It is important to remember that the parallel host
interface requires the DATA[7:0] pins of the
CS493XX. The external memory interface also
requires the DATA[7:0] pins so the Parallel host
control modes can only be used if external memory
is not required.
Mnemonic
Chip Select
Pin Name Pin Number
CS
18
4
Write Enable
Output Enable
Register Address Bit 1
Register Address Bit 0
Interrupt Request
DATA7
WR
RD
5
A1
6
A detailed description for each parallel host mode
will now be given. The following information will
be provided for the Intel mode and Motorola mode:
A0
7
INTREQ
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
19
8
DATA6
9
•
•
•
The pins of the CS493XX which must be used
for proper communication
DATA5
DATA4
10
11
14
15
16
17
Flow diagram and description for a parallel
byte write
DATA3
DATA2
DATA1
Flow diagram and description for a parallel
byte read
DATA0
Table 6. Intel Mode Communication Signals
The four registers of the CS493XX’s parallel host
mode are not used identically. The algorithm used
for communicating with each register will be given
as a functional description, building upon the basic
read and write protocols defined in the Motorola
and Intel sections. The following will be covered:
conditions such as a change in the incoming audio
data type (e.g. PCM --> AC-3).
DS339PP4
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