CS49300 Family DSP
the host ends the write cycle by driving the CS
and WR pins high.
6.2.1.1.Writing a Byte in Intel Mode
Information provided in this section is intended as
a functional description of how to write control
information to the CS493XX. The system designer
must insure that all of the timing constraints of the
Intel Parallel Host Mode Write Cycle are met.
6.2.1.2.Reading a Byte in Intel Mode
Information provided in this section is intended as
a functional description of how to write control
information to the CS493XX. The system designer
must insure that all of the timing constraints of the
Intel Parallel Host Mode Read Cycle are met.
The flow diagram shown in Figure 24 illustrates
the sequence of events that define a one-byte write
in Intel mode. The protocol presented in Figure 24
will now be described in detail.
The flow diagram shown in Figure 25 illustrates
the sequence of events that define a one-byte read
in Intel mode. The protocol presented in Figure 25
will now be described in detail.
1) The host must first drive the A1 and A0 register
address pins of the CS493XX with the address
of the desired Parallel I/O Register.
1) The host must first drive the A1 and A0 register
address pins of the CS493XX with the address
of the desired Parallel I/O Register. Note that
only the Host Message register and the Host
Control register can be read.
Host Message: A[1:0]==00b.
Host Control:
PCMDATA:
CMPDATA:
A[1:0]==01b.
A[1:0]==10b.
A[1:0]==11b.
Host Message: A[1:0]==00b.
2) The host then indicates that the selected register
will be written. The host initiates a write cycle
by driving the CS and WR pins low.
Host Control:
A[1:0]==01b.
2) The host now indicates that the selected register
will be read. The host initiates a read cycle by
driving the CS and RD pins low.
3) The host drives the data byte to the DATA[7:0]
pins of the CS493XX.
3) Once the data is valid, the host can read the
value of the selected register from the
DATA[7:0] pins of the CS493XX.
4) Once the setup time for the write has been met,
ADDRESS A PARALLEL I/O REGISTER
(A[1:0] SET APPROPRIATELY
ADDRESS A PARALLEL I/O REGISTER
(A[1:0] SET APPROPRIATELY
CS (LOW )
W R (LO W )
CS (LOW )
RD (LOW )
WRITE BYTE TO
DATA [7:0]
READ BYTE FROM
DATA [7:0]
CS (HIGH)
RD (HIGH)
CS (HIGH)
WR (HIGH)
Figure 24. Intel Mode, One-Byte Write Flow Diagram
Figure 25. Intel Mode, One-Byte Read Flow Diagram
44
DS339PP4
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