CS4923/4/5/6/7/8/9
covered in the CS4923/4/5/6/7/8/9 Hardware
each signal on the CS4923/4/5/6/7/8/9. RD and
User’s Guide. Application configuration is WR have no effect when CS is held high.
described in the application code user’s guide for
the code being used.
When the DSP writes a byte to the HOSTMSG
register, the HOUTRDY bit in the CONTROL
register is set to indicate that there is data to be
6.2 Parallel Host Interface
read. To initiate a read cycle the host should drive
The byte wide parallel host interface of the
CS low. When CS is low, RD becomes the output
CS492X supports application code download,
enable for DATA[7:0]. When CS and RD are low,
communication for hardware and application
the contents of register address A[1:0] are driven
configuration, compressed data input, and PCM
on the DATA[7:0] bus. The address A[1:0] must be
data input. When using either Intel or Motorola
valid a minimum time before either CS or RD goes
modes, the parallel interface is implemented using
low. The HOUTRDY bit of the CONTROL
four 8-bit internal registers which are selectable
register is cleared after the host reads from the
using inputs A1 and A0 as shown in table 3. Table
HOSTMSG register.
5 shows the individual registers and their bit
mapping.
Driving both CS and WR low begins an 8-bit write
cycle. The address A[1:0] must be valid a
minimum time before either CS or WR goes low.
On the first rising edge of CS or WR, the write
cycle ends and DATA[7:0] are latched internally
by the CS492X. Data must be held sufficiently to
satisfy the hold time as given in the timing section.
The HINBSY bit is set when the host writes the
HOSTMSG register. This bit is cleared when the
byte in the HOSTMSG register is read by the DSP.
In either the Intel or Motorola mode the INTREQ
pin can be used to interrupt the host when the DSP
has unsolicited outgoing messages to be read. For
specific details on the behavior of INTREQ in one
of the parallel modes, please see the
CS4923/4/5/6/7/8/9 Hardware User’s Guide.
A1
A0 Register Name Register Function
(Pin 6) (Pin 7)
During RESET low, all control signals have no
effect and DATA[7:0] are high impedance.
1
1
0
0
1
0
1
0
CMPDATA
PCMDATA
8-bit compressed
data to input unit
(write only)
8-bit linear PCM data
to input unit (write
only)
Pin Name
CS
RD
WR
A1
Pin Description
Chip Select
Pin Number
18
5
4
6
7
20
8
9
10
11
14
15
16
17
Output Enable
Write Enable
Register Address 1
Register Address 0
Interrupt Request
Data Bit 7
CONTROL Multi-bit control regis-
ter for setup and
handshaking (R/W)
HOSTMSG 8-bit control pipe
message register
A0
INTREQ
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
(R/W)
Data Bit 6
Data Bit 5
Data Bit 4
Data Bit 3
Data Bit 2
Data Bit 1
Data Bit 0
Table 3. Host Memory Map
6.2.1 Intel Parallel Host Mode
Intel parallel host mode is accomplished with CS,
RD, WR, A[1:0], and DATA[7:0]. Table 4 shows
the pin name, pin description and pin number of
Table 4. Intel Parallel Host Mode Pin Assignments
34
DS262F2
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