CS4923/4/5/6/7/8/9
The PLL reference clock has three possible sources
that are routed through a multiplexer controlled by
the DSP: SCLKN2, SCLKN1, and CLKIN.
Typically, in audio/video environments like set-top
boxes, the CLKIN pin is connected to 27 MHz. In
other scenarios such as an A/V receiver design, the
PLL can be clocked through the CLKIN pin with
even multiples of the desired sampling rate or with
an already available clock source. CLKIN is
typically a multiple of a standard sampling
frequency in this scenario (e.g. 11.2896 MHz).
5. CLOCKING
Revision D of the CS4923/4/5/6/7/8/9 also
incorporates a programmable phase locked loop
(PLL) clock synthesizer. The PLL takes an input
reference clock and produces all the internal clocks
required to run the internal DSP and to provide
master mode timing to the audio input/output
peripherals. The clock manager also includes a
33-bit system time clock (STC) to support audio
and video synchronization in broadcast
applications.
The clock manager is controlled by the DSP
application software. Please refer to the Hardware
User’s Guide for the CS4923/4/5/6/7/8/9 (AN115)
and all relevant application code user’s guides for
information on supported CLKIN frequencies and
how to set up and control the internal PLL.
The PLL can be internally bypassed by connecting
the CLKSEL pin to VD. This connection
multiplexes the CLKIN pin directly to the DSP
clock. Care should be taken to note the minimum
CLKIN requirements when bypassing the PLL.
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DS262F2
CIRRUS [ CIRRUS LOGIC ]
