CS4923/4/5/6/7/8/9
CS4926 or CS4928 for DTS decode. An image of
the DTS tables is available from the factory.
6. CONTROL
Control of the CS4923/4/5/6/7/8/9 can be
accomplished through one of four methods. The
CS492X supports I C and SPI serial
Below is a brief discussion of each of the
communication modes available for the
2
communication. In addition the CS492X supports CS4923/4/5/6/7/8/9. For a complete description of
both a Motorola and Intel byte wide parallel host these communication modes along with flow
control mode. Only one of the four communication charts, pseudocode and restrictions, please consult
modes can be selected for control. The states of the the CS4923/4/5/6/7/8/9 Hardware User’s Guide. A
RD, WR, and PSEL pins at the rising edge of complete understanding of the decoder and its
RESET determine the interface type as shown in operation can not be accomplished without
table 2.
consulting the CS4923/4/5/6/7/8/9 Hardware
User’s Guide and the application code user’s
guides.
RD
WR
PSEL
Host Interface Mode
(Pin 5) (Pin 4) (Pin 19)
6.1 Boot and Control Mode Overview
1
1
0
1
1
1
1
0
X
8-bit Motorola
8-bit Intel
Serial I2C
Regardless of which communication mode is used,
the CS4923/4/5/6/7/8/9 must be booted and loaded
with code at run time. The general sequence from a
hardware perspective is as follows:
1
0
X
Serial SPI
Table 2. Host Modes
5) RESET Low
Whichever host communication mode is used, host
control of the CS4923/4/5/6/7/8/9 is handled
through the application software running on the
DSP. Configuration and control of the CS492X
decoder and its peripherals are indirectly executed
through a messaging protocol supported by the
downloaded application code. In other words
successful communication can only be
accomplished by following the low level hardware
communication format and high level messaging
protocol. The specifications of the messaging
protocol can be found in any of the application
code user’s guides.
6) Set Communication Configuration Pins
7) RESET High
8) Download Code
9) Configure Hardware
10) Configure Application Code
11) Kickstart the Decoder
The host has three options for code download:
•
•
•
Parallel Download through the parallel host in-
terface
2
Serial download through either the SPI or I C
interface
It should be noted that when using the CS4926 or
CS4928 for DTS decoding, an external memory
interface must be used for DTS tables that are
required for decoding. (see section 6.5 for
information on external memory). The external
memory interface and the parallel interface modes
can not be used together. For this reason the system
designer must use one of the serial communication
modes with external memory if designing with the
Autoboot with external memory when using a
serial communication mode.
Once again the CS4923/4/5/6/7/8/9 Hardware
User’s Guide should be consulted for a complete
description of the boot and download procedure
including
the
necessary
communication
handshaking. Hardware configuration is also
DS262F2
33
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