CS4923/4/5/6/7/8/9
and a 1uF capacitor as close as physically possible
to each power pin. The 0.1uF capacitor should be
closest to the device (typically 5mm or closer).
4. POWER
The CS492X requires a 3.3V digital power supply
for the digital logic within the DSP and a 3.3V
analog power supply for the internal PLL. There
are three digital power pins, VD1, VD2 and VD3,
along with three digital grounds, DGND1, DGND2
and DGND3. There is one analog power pin, VA
and one analog ground, AGND. The DSP will
perform at its best when noise has been eliminated
from the power supply. The recommendations
given below for decoupling and power
conditioning of the CS492X will help to ensure
reliable performance.
4.2 Analog Power Conditioning
In order to obtain the best performance from the
CS4923/4/5/6/7/8/9’s internal PLL, the analog
power supply (VA) must be as clean as possible. A
ferrite bead should be used to filter the 3.3V power
supply for the analog portion of the CS492X. This
power scheme is shown in the typical connection
diagrams.
4.3 Pads
Revision D and all subsequent revisions
incorporate 5V tolerant pads. This means that while
the CS492X power supplies require 3.3 volts, 5 volt
signals can be applied to the inputs without
damaging the part.
4.1 Decoupling
It is good practice to decouple noise from the
power supply by placing capacitors directly
between the power and ground of the CS492X.
Each pair of power pins (VD1/DGND,
VD2/DGND, VD3/DGND, VA/AGND) should
have its own decoupling capacitors. The
recommended procedure is to place both a 0.1uF
The I/O pads for Revision B of the CS4923/4/5/6
are not 5 volt tolerant. Input levels for revision B of
the CS4923/4/5/6 should be no greater than 3.3
DS262F2
31
CIRRUS [ CIRRUS LOGIC ]
