SCCLK
SCDIN
CS
AD6 AD5 AD4 AD3 AD2 AD1 AD0 R/W D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
SPI Write Functional Timing
SCCLK
SCDIN
AD6 AD5 AD4 AD3 AD2 AD1 AD0 R/W
SCDOUT
CS
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
INTREQ
Note 1
Note 2
SPI Read Functional Timing
Notes: 1. INTREQ is guaranteed to stay low until the rising edge of SCCLK for the second to last bit of
the last byte to be transferred out of the CS4923/4/5/6/7/8/9
2. INTREQ is guaranteed to stay high until the next rising edge of SCCLK at which point it may
go low again if there is new data to be read. The condition of INTREQ going low at this point
should be treated as a new read condition and a new start condition followed by an address
byte should be sent
Figure 19. SPI Timing
CIRRUS [ CIRRUS LOGIC ]
