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CS42448-DQZ 参数 Datasheet PDF下载

CS42448-DQZ图片预览
型号: CS42448-DQZ
PDF下载: 下载PDF文件 查看货源
内容描述: 108分贝192千赫6英寸,8出CODEC [108 dB, 192 kHz 6-in, 8-out CODEC]
分类和应用:
文件页数/大小: 70 页 / 1151 K
品牌: CIRRUS [ CIRRUS LOGIC ]
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6.3  
POWER CONTROL (ADDRESS 02H)  
7
6
5
4
3
2
1
0
PDN_ADC3  
PDN_ADC2  
PDN_ADC1  
PDN_DAC4  
PDN_DAC3  
PDN_DAC2  
PDN_DAC1  
PDN  
6.3.1 POWER DOWN ADC PAIRS(PDN_ADCX)  
Default = 0  
0 - Disable  
1 - Enable  
Function:  
When enabled, the respective ADC channel pair (ADC1 - AIN1/AIN2; ADC2 - AIN3/AIN4; and ADC3  
- AIN5/AIN6) will remain in a reset state.  
6.3.2 POWER DOWN DAC PAIRS (PDN_DACX)  
Default = 0  
0 - Disable  
1 - Enable  
Function:  
When enabled, the respective DAC channel pair (DAC1 - AOUT1/AOUT2; DAC2 - AOUT3/AOUT4;  
DAC3 - AOUT5/AOUT6; and DAC4 - AOUT7/AOUT8) will remain in a reset state. It is advised that  
any change of these bits be made while the DACs are muted or the power down bit (PDN) is enabled  
to eliminate the possibility of audible artifacts.  
6.3.3 POWER DOWN (PDN)  
Default = 0  
0 - Disable  
1 - Enable  
Function:  
The entire device will enter a low-power state when this function is enabled. The contents of the con-  
trol registers are retained in this mode.  
DS648PP2  
45  
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