6.6
ADC CONTROL & DAC DE-EMPHASIS (ADDRESS 05H)
7
6
5
4
3
2
1
0
ADC1-2_HPF
FREEZE
ADC3_HPF
FREEZE
DAC_DEM
ADC1
SINGLE
ADC2
SINGLE
ADC3
SINGLE
AIN5_MUX
AIN6_MUX
6.6.1 ADC1-2 HIGH PASS FILTER FREEZE (ADC1-2_HPF FREEZE)
Default = 0
Function:
When this bit is set, the internal high-pass filter will be disabled for ADC1 and ADC2.The current DC
offset value will be frozen and continue to be subtracted from the conversion result. See “ADC Digital
Filter Characteristics” on page 14.
6.6.2 ADC3 HIGH PASS FILTER FREEZE (ADC3_HPF FREEZE)
Default = 0
Function:
When this bit is set, the internal high-pass filter will be disabled for ADC3.The current DC offset value
will be frozen and continue to be subtracted from the conversion result. See “ADC Digital Filter Char-
acteristics” on page 14.
6.6.3 DAC DE-EMPHASIS CONTROL (DAC_DEM)
Default = 0
0 - No De-Emphasis
1 - De-Emphasis Enabled (Auto-Detect Fs)
Function:
Enables the digital filter to maintain the standard 15µs/50µs digital de-emphasis filter response at the
auto-detected sample rate of either 32, 44.1, or 48 kHz. De-emphasis will not be enabled, regardless
of this register setting, at any other sample rate.
6.6.4 ADC1 SINGLE-ENDED MODE (ADC1 SINGLE)
Default = 0
0 - Disabled; Differential input to ADC1
1 - Enabled; Single-Ended input to ADC1
Function:
When enabled, this bit allows the user to apply a single-ended input to the positive terminal of ADC1.
+6 dB digital gain is automatically applied to the serial audio data of ADC1. The negative leg must be
driven to the common mode of the ADC. See Figure 27 on page 56 for a graphical description.
6.6.5 ADC2 SINGLE-ENDED MODE (ADC2 SINGLE)
Default = 0
0 - Disabled; Differential input to ADC2
1 - Enabled; Single-Ended input to ADC2
DS648PP2
49
CIRRUS [ CIRRUS LOGIC ]
