CS42406
4.3.1a
Stand Alone Mode
The desired format for the DAC serial port is selected via the DIF1 and DIF0 pins. For an illustration of the
required relationship between the DAC_LRCK, DAC_SCLK and SDINx, see Figures 28-30.
DIF1
DIF0
DESCRIPTION
Left Justified, up to 24-bit Data
I²S, up to 24-bit Data
Right Justified, 16-bit Data
Right Justified, 24-bit Data
FORMAT
FIGURE
29
0
0
1
1
0
1
0
1
0
1
2
3
28
30
30
Table 6. DAC Digital Interface Format - Stand Alone Mode
4.3.1b
Control Port Mode
The desired format for the DAC serial port is selected via the DIF2, DIF1 and DIF0 bits in the Mode Control
2 register (see section 6.1.2). For an illustration of the required relationship between DAC_LRCK,
DAC_SCLK and SDINx, see Figures 28-30.
4.3.2
ADC Serial Port
The CS42406 ADC serial port supports both I²S and Left Justified serial audio formats. Upon start-up, the CS42406
will detect the logic level on SDOUT. A 10 kΩ pull-up resistor to VLS is needed to select I²S format, and a 10 kΩ
pull-down resistor to GND is needed to select Left Justified format. Please see Figures 28 and 29 for an illustration
of the required relationship between ADC_LRCK, ADC_SCLK, and SDOUT.
4.4
De-Emphasis Control
The CS42406 includes on-chip digital de-emphasis. Figure 35 shows the de-emphasis curve for Fs equal
to 44.1 kHz. The frequency response of the de-emphasis curve will scale proportionally with changes in
sample rate, Fs.
Gain
dB
T1=50 µs
0dB
T2 = 15 µs
-10dB
F1
3.183 kHz
F2
10.61 kHz
Frequency
Figure 35. De-Emphasis Curve
Notes: De-emphasis is only available in Single-Speed Mode.
4.4.1
Stand Alone Mode
The operational mode pins, DAC_M1 and DAC_M0, selects the 44.1 kHz de-emphasis filter. Please see
section 4.1.2a for the desired de-emphasis control.
4.4.2
Control Port Mode
The Mode Control bits selects either the 32, 44.1, or 48 kHz de-emphasis filter. Please see section 6.1.3
for the desired de-emphasis control.
36
DS614PP2
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