CS42406
÷ 1
÷ 2
0
1
Single
Speed
÷ 256
00
ADC_LRCK
Output
(Equal to Fsout
Double
Speed
÷ 128
÷ 64
01
10
)
Quad
Speed
Auto-Select
0
1
MCLK
ADC_M1
ADC_M0
Single
Speed
÷ 4
00
÷ 1.5
÷ 3
0
1
ADC_SCLK
Output
Double
Speed
÷ 2
÷ 1
01
10
Quad
Speed
ADC_384x/256x
Auto-Select
Figure 34. ADC Serial Port, Master Mode Clocking
4.2.2 Operation as a Clock Slave
ADC_LRCK and ADC_SCLK operate as inputs in clock slave mode. It is recommended that the left/right clock be
synchronously derived from the master clock and must be equal to Fs. It is also recommended that the serial clock
be synchronously derived from the master clock and be equal to 64x Fs to maximize system performance.
A unique feature of the CS42406 ADC serial port is the automatic selection of either Single, Double or Quad-Speed
Mode when operating as a clock slave. The auto-mode selection feature supports all standard audio sample rates
from 2 to 200 kHz. However, there are ranges of non-standard audio sample rates that are not supported when op-
erating with a fast MCLK (512x/768x, 256x/384x, 128x/192x for Single, Double, and Quad-Speed Modes, respec-
tively). Please refer to Table 1 and Table 2 for supported sample rate ranges.
4.3
Digital Interface Format
DAC Serial Port
4.3.1
The CS42406 DAC serial port will accept audio samples in 1 of 4 digital interface formats in Stand Alone
Mode, as illustrated in Table 6, and 1 of 6 formats in Control Port mode, as illustrated in Table 7 on page
44.
35
CIRRUS [ CIRRUS LOGIC ]
