CS42406
power-down state is related to the value of the DC-blocking capacitance and the output load. For example,
with a 3.3 µF capacitor, the minimum power-down time will be approximately 0.4 seconds.
4.8
Mute Control
The Mute Control pins go high during power-up initialization, reset, muting (see section 6.1.1 and 6.4.1),
or if the MCLK to DAC_LRCK ratio is incorrect. These pins are intended to be used as control for external
mute circuits to prevent the clicks and pops that can occur in any single-ended single supply system.
Use of the Mute Control function is not mandatory but recommended for designs requiring the absolute
minimum in extraneous clicks and pops. Also, use of the Mute Control function can enable the system
designer to achieve idle channel noise/signal-to-noise ratios which are only limited by the external mute
circuit. Please see the CDB42406 data sheet for a suggested mute circuit.
4.9
Grounding and Power Supply Arrangements
As with any high resolution converter, the CS42406 requires careful attention to power supply and ground-
ing arrangements if its potential performance is to be realized. Figure 33 shows the recommended power
arrangements, with VA, VD, VLS and VLC connected to clean supplies. If the ground planes are split be-
tween digital ground and analog ground, the GND pins of the CS42406 should be connected to the analog
ground plane.
All signals, especially clocks, should be kept away from the FILT+ and VQ pins in order to avoid unwanted
coupling into the modulators. The CDB42406 evaluation board demonstrates the optimum layout and
power supply arrangements.
4.9.1
Capacitor Placement
Decoupling capacitors should be placed as close to the CS42406 as possible, with the low value ceramic
capacitor being the closest. To further minimize impedance, these capacitors should be located on the
same layer as the converter. If desired, all supply pins may be connected to the same supply, but a de-
coupling capacitor should still be placed on each supply pin and referenced to analog ground. Due to the
proximity of the two VD pins (pins 7 and 9), one set of decoupling capacitors will be sufficient for the digital
supply. Please refer to Figure 33.
4.10 Control Port Interface
The control port is used to load all the internal register settings (see section 6). The operation of the control
port may be completely asynchronous with the audio sample rate. However, to avoid potential interfer-
ence problems, the control port pins should remain static if no operation is required.
The control port operates in one of two modes: I²C or SPI.
Notes: MCLK must be applied during all I²C communication.
4.10.1
Memory Address Pointer (MAP)
The MAP byte precedes the control port register byte during a write operation and is not available again
until after a start condition is initiated. During a read operation the byte transmitted after the ACK will con-
tain the data of the register pointed to by the MAP (see sections 4.10.2a and 4.10.2b for write/read de-
tails).
7
INCR
0
6
Reserved
0
5
Reserved
0
4
Reserved
0
3
MAP3
0
2
MAP2
0
1
MAP1
0
0
MAP0
0
39
CIRRUS [ CIRRUS LOGIC ]
