CL-PS7500FE
System-on-a-Chip for Internet Appliance
10.3.65 VIDINITB (0x1E8) — Duplex LCD Video DMA INIT B
31
30
29 28
4
3
0
L
E
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
0 0 0 0
X
For normal CRT displays and single-panel LCD data, only the A registers are used. Program this register
with to‘0’s. For dual-panel displays, load this register with the address of the first qword in the frame buffer
to be displayed at the top left of the lower panel. Set the last bit (30) only if the INIT B register is pro-
grammed to the same value as the VIDEND register.
I
initial fetch location B
bits[31,29] unused
bit[30] last bit
Write
0
1
not last fetch location
last fetch location
bits[28:4] video initial B DMA fetch location
bits[3:0] ignored
bit[31] ‘0’
Read
bit[30] last bit
0
1
not last fetch location
last fetch location
bit[29] ‘equal’ – output of comparator
bits[28:4] video initial B DMA fetch location
bits[3:0] always ‘0’
June 1997
107
ADVANCE DATA BOOK v2.0
MEMORY AND I/O PROGRAMMERS’ MODEL
CIRRUS [ CIRRUS LOGIC ]
