CL-PD6710/’22
ISA–to–PC-Card Host Adapters
15.3.2 Reset Timing
Table 15-8. Reset Timing
Symbol
Parameter
MIN
500
500
500
MAX
Units
ns
t
t
t
PWRGOOD generated reset pulse width
1
2
3
1
Clock active before end of reset
ns
End of PWRGOOD generated reset to first Command
ns
1
Clock input must be active for a minimum of 500 ns before PWRGOOD goes active to allow sufficient internal clocks to
initialize internal circuitry.
t
1
PWRGOOD
t
2
CLK
MEMR*, MEMW*
IOR*, IOW*
t
3
Figure 15-2. Reset Timing
94
May 1997
ELECTRICAL SPECIFICATIONS
PRELIMINARY DATA SHEET v3.1