CL-PD6710/’22
ISA–to–PC-Card Host Adapters
15.3.1 ISA Bus Timing
Table 15-7. ISA Bus Timing
Symbol
Parameter
MIN
MAX
Unit
ns
t
MEMCS16* active delay from LA[23:17] valid
LA[23:17] setup to ALE inactive
40
1
t
30
5
ns
1a
1b
t
LA[23:17] hold from ALE inactive
ns
1
t
IOCS16* active delay from SA[15:0]
40
40
ns
2
1
t
IOCS16* inactive delay from SA[15:0]
ns
2a
1, 2
t
SA[16:0], SBHE* setup to any Command active
30
90
ns
ns
3
4
LA[23:17] latching by ALE to any Command active
3
t
Any Command active to IOCHRDY inactive (low)
40
30
40
ns
4
t
IOCHRDY three-state from Command inactive
5
4a
t
MEMCS16* inactive delay from unlatched LA[23:17]
ns
ns
ns
ns
ns
5
1
t
IOW* or IOR* pulse width
140
180
100
0
6a
6b
1
t
MEMW* or MEMR* pulse width
t
t
t
Any Command inactive to next Command active
Address or SBHE* hold from any Command inactive
7
8
9
5
Data valid from MEMW* active
40
40
ns
ns
Data valid from IOW* active
t
Data hold from MEMW* inactive
Data hold from IOW* inactive
5
5
ns
ns
10
t
t
t
t
t
t
t
t
t
t
Data delay from IOR* active, for internal registers
Data delay from IOCHRDY active
0
130
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
11
12
13
14
15
16
17
18
19
20
Data hold from IOR* or MEMR* inactive
AEN inactive setup to valid IOR* or IOW* active
AEN hold from IOR* or IOW* inactive
0
40
5
30
REFRESH* inactive setup to valid MEMR* or MEMW* active
REFRESH* inactive hold from MEMR* or MEMW* active
MEMCS16* active delay from SA[16:12] valid
*ZWS delay from MEMW* active
40
0
40
30
15
*ZWS hold from MEMW* inactive
1
2
3
4
5
AEN must be inactive for t , t , and t timing specifications to be applicable.
2
3
6
Command is defined as IOR*, IOW*, MEMR*, or MEMW*.
Except for valid card memory writes, which are zero wait state when internal write FIFO is not full.
If card is removed during a card access cycle, IOCHRDY is three-stated without waiting for end of Command.
Based on 25-MHz internal clock, produced either by an internal synthesizer and 14.318-MHz signal applied to CLK pin,
or by supplying 25 MHz directly to CLK pin and bypassing the internal synthesizer.
92
May 1997
ELECTRICAL SPECIFICATIONS
PRELIMINARY DATA SHEET v3.1
CIRRUS [ CIRRUS LOGIC ]
