CL-PD6710/’22
ISA–to–PC-Card Host Adapters
15.3.6 PC Card Bus Timing Calculations
Calculations for minimum PC Card cycle Setup, Command, and Recovery timings are made by first cal-
culating factors derived from the applicable timer set’s timing registers and then by applying the factor to
an equation relating it to the internal clock period.
The PC Card cycle timing factors, in terms of the number of internal clocks, are calculated as follows:
S = (N
× N ) + 1
Equation 15-1
Equation 15-2
Equation 15-3
pres
val
C = (N
× N ) + 1
val
pres
pres
R = (N
× N ) + 1
val
N
and N are the specific selected prescaler and multiplier value from the timer set’s Setup, Com-
val
pres
mand, and Recovery Timing registers (see Chapter 10 for a description of these registers).
From this, a PC Card cycle’s Setup, Command, and Recovery time for the selected timer set are calcu-
lated as follows:
Setup time = (S × Tcp) ± 10 ns
Command time = (C × Tcp) ± 10 ns
Equation 15-4
Equation 15-5
Equation 15-6
Recovery time = (R × Tcp) ± 10 ns
When the internal synthesizer is used, the calculation of the internal clock period Tcp is:
Tcp = T
× 4/7
Equation 15-7
CLKP
where T
is the period of the clock supplied to the CLK input pin. An input frequency of 14.318 MHz
CLKP
at the CLK input pin results in an internal clock period of Tcp = 40 ns.
When the internal synthesizer is bypassed, Tcp = T . An input frequency of 25 MHz in this circum-
CLKP
stance would also result in an internal clock period of Tcp = 40 ns.
The timing diagrams that follow were derived for a CL-PD67XX using the internal synthesizer and a
14.318-MHz CLK pin input. The internal clock frequency of the CL-PD67XX is 7/4 of this incoming signal
(Tcp = 40 ns). The examples are for the default values of the Timing registers for Timer Set 0, as follows:
Timing Register Name
(Timer Set 0)
Value
(Default)
Resultant
Resultant
Index
N
N
pres
val
Setup Timing 0
3Ah
3Bh
3Ch
01h
06h
03h
1
1
6
3
Command Timing 0
Recovery Timing 0
1
1
Thus the minimum times for the default values are as follows:
Default minimum Setup time = (S × Tcp) – 10 ns = {2 × 40 ns} – 10 ns = 70 ns
Equation 15-8
98
May 1997
ELECTRICAL SPECIFICATIONS
PRELIMINARY DATA SHEET v3.1
CIRRUS [ CIRRUS LOGIC ]
