CL-PD6710/’22
ISA–to–PC-Card Host Adapters
15.3.5 Input Clock Specification
Table 15-11.Input Clock Specification
Symbol
Parameter
CLK pin input rise time
CLK pin input fall time
CLK input low period
CLK input high period
MIN
MAX
Units
ns
Conditions
t
t
t
t
1
1
7
7
1
2
3
4
ns
0.4 T
0.6 T
ns
CLKP
CLKP
CLKP
CLKP
0.4 T
0.6 T
ns
V
Center voltage at which
period specified
0.5 V
0.5 V
DD
V
center
DD
T
T
V
Input clock period,
internal clock
69.84 – 0.1%
40 – 0.1%
2.0
69.84 + 0.1%
40 + 0.1%
ns
ns
Normal synthesizer
CLKP
CLKP
operation. Misc Control
2 register, bit 0 = ‘0’.
CLK pin at 14.318 MHz.
Input clock period,
external clock
Synthesizer bypassed.
Misc Control 2 register,
bit 0 = ‘1’.
CLK pin at 25 MHz.
CLK input high voltage
CLK input low voltage
CLK input high voltage
CLK input low voltage
V
V
V
V
CORE_VDD = 3.0 V
CORE_VDD = 3.6 V
CORE_VDD = 4.5 V
CORE_VDD = 5.5 V
IHmin
ILmax
V
0.8
V
0.7 V
DD
IHCmin
ILCmax
V
0.2 V
DD
t
1
t
2
V
, V
IHmin IHCmin
V
center
V
, V
ILmax ILCmax
CLK
t
t
4
3
T
CLKP
Figure 15-5. Input Clock Specification
May 1997
97
PRELIMINARY DATA SHEET v3.1
ELECTRICAL SPECIFICATIONS
CIRRUS [ CIRRUS LOGIC ]
