CL-PD6710/’22
ISA–to–PC-Card Host Adapters
15.3 AC Timing Specifications
This section includes system timing requirements for the CL-PD67XX. Timings are provided in nanosec-
onds (ns), at TTL input levels, with the ambient temperature varying from 0°C to 70°C, and V varying
CC
from 3.0 to 3.6 V or 4.5 to 5.5 V DC. The AT bus speed is 10 MHz unless otherwise noted. Note that an
asterisk (*) denotes an active-low signal for the ISA bus interface, and a dash (-) denotes an active-low
signal for the PC Card socket interface.
Additionally, the following statements are true for all timing information:
● All timings assume a load of 50 pF.
● TTL signals are measured at TTL threshold; CMOS signals are measured at CMOS threshold.
Table 15-6. List of AC Timing Specifications
Title
Page Number
Table 15-7. ISA Bus Timing
92
94
Table 15-8. Reset Timing
Table 15-9. Pulse Mode Interrupt Timing
95
Table 15-10. General-Purpose Strobe Timing
Table 15-11. Input Clock Specification
96
97
Table 15-12. Memory Read/Write Timing (Word Access)
Table 15-13. Word I/O Read/Write Timing
99
100
102
103
104
105
107
109
Table 15-14. PC Card Read/Write Timing when System Is 8-Bit
Table 15-15. Normal Byte Read/Write Timing
Table 15-16. 16-Bit System to 8-Bit I/O Card: Odd Byte Timing
Table 15-17. DMA Read Cycle Timing (CL-PD6722 only)
Table 15-18. DMA Write Cycle Timing (CL-PD6722 only)
Table 15-19. DMA Request Timing (CL-PD6722 only)
May 1997
91
PRELIMINARY DATA SHEET v3.1
ELECTRICAL SPECIFICATIONS
CIRRUS [ CIRRUS LOGIC ]
