CL-PD6710/’22
ISA–to–PC-Card Host Adapters
6.7 Mapping Enable
Register Name: Mapping Enable
Index: 06h
Register Per: socket
Register Compatibility Type: 365
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
I/O Map 1
Enable
I/O Map 0
Enable
MEMCS16 Full Memory Map 4 Memory Map 3 Memory Map 2 Memory Map 1 Memory Map 0
Decode
RW:0
Enable
RW:0
Enable
RW:0
Enable
RW:0
Enable
RW:0
Enable
RW:0
RW:0
RW:0
Bit 0 — Memory Map 0 Enable
0
1
Memory Mapping registers for Memory Space 0 disabled.
Memory Mapping registers for Memory Space 0 enabled.
When this bit is ‘1’, the Memory Mapping registers for Memory Space 0 will be enabled and the
controller will respond to memory accesses in the memory space defined by those registers.
Bit 1 — Memory Map 1 Enable
0
1
Memory Mapping registers for Memory Space 1 disabled.
Memory Mapping registers for Memory Space 1 enabled.
When this bit is ‘1’, the Memory Mapping registers for Memory Space 1 will be enabled and the
controller will respond to memory accesses in the memory space defined by those registers.
Bit 2 — Memory Map 2 Enable
0
1
Memory Mapping registers for Memory Space 2 disabled.
Memory Mapping registers for Memory Space 2 enabled.
When this bit is ‘1’, the Memory Mapping registers for Memory Space 2 will be enabled and the
controller will respond to memory accesses in the memory space defined by those registers.
Bit 3 — Memory Map 3 Enable
0
1
Memory Mapping registers for Memory Space 3 disabled.
Memory Mapping registers for Memory Space 3 enabled.
When this bit is ‘1’, the Memory Mapping registers for Memory Space 3 will be enabled and the
controller will respond to memory accesses in the memory space defined by those registers.
Bit 4 — Memory Map 4 Enable
0
1
Memory Mapping registers for Memory Space 4 disabled.
Memory Mapping registers for Memory Space 4 enabled.
When this bit is ‘1’, the Memory Mapping registers for Memory Space 4 will be enabled and the
controller will respond to memory accesses in the memory space defined by those registers.
Bit 5 — MEMCS16 Full Decode
This bit is not used. All addresses are used to determine the level of MEMCS16*.
May 1997
47
PRELIMINARY DATA SHEET v3.1
CHIP CONTROL REGISTERS
CIRRUS [ CIRRUS LOGIC ]
