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CL-PD6710-VC-A 参数 Datasheet PDF下载

CL-PD6710-VC-A图片预览
型号: CL-PD6710-VC-A
PDF下载: 下载PDF文件 查看货源
内容描述: [PCMCIA Bus Controller, MOS, PQFP144, VQFP-144]
分类和应用: PC
文件页数/大小: 128 页 / 1552 K
品牌: CIRRUS [ CIRRUS LOGIC ]
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CL-PD6710/’22  
ISA–to–PC-Card Host Adapters  
6.6 Management Interrupt Configuration  
Register Name: Management Interrupt Configuration  
Index: 05h  
Register Per: socket  
Register Compatibility Type: 365  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Battery Dead  
Or Status  
Change  
Battery  
Warning  
Enable  
Card Detect  
Enable  
Management IRQ Select  
RW:0000  
Ready Enable  
RW:0  
Enable  
RW:0  
RW:0  
RW:0  
This register controls which status changes may cause management interrupts and at which pin the man-  
agement interrupts will appear.  
Bit 0 — Battery Dead Or Status Change Enable  
0
1
Battery Dead Or Status Change management interrupt disabled.  
If Battery Dead Or Status Change is ‘1’, a management interrupt will occur.  
When this bit is ‘1’, a management interrupt will occur when the Card Status Change register’s  
Battery Dead Or Status Change bit (see page 44) is ‘1’. This allows management interrupts to be  
generated on changes in level of the BVD1/-STSCHG pin.  
Bit 1 — Battery Warning Enable  
0
1
Battery Warning Change management interrupt disabled.  
If Battery Warning Change is ‘1’, a management interrupt will occur.  
When this bit is ‘1’, a management interrupt will occur when the Card Status Change register’s  
Battery Warning Change bit (see page 44) is ‘1’.This bit is ignored when the card socket is in I/O  
mode.  
Bit 2 — Ready Enable  
0
Ready Change management interrupt disabled.  
If Ready Change is ‘1’, a management interrupt will occur.  
1
When this bit is ‘1’, a management interrupt will occur when the Card Status Change register’s  
Ready Change bit (see page 44) is ‘1’.  
Bit 3 — Card Detect Enable  
0
Card Detect Change management interrupt disabled.  
If Card Detect Change is ‘1’, a management interrupt will occur.  
1
When this bit is ‘1’, a management interrupt will occur when the Card Status Change register’s  
Card Detect Change bit (see page 44) is ‘1’.  
May 1997  
45  
PRELIMINARY DATA SHEET v3.1  
CHIP CONTROL REGISTERS