CL-PD6710/’22
ISA–to–PC-Card Host Adapters
Bit 7 — Timing Register Select 1
0
1
Accesses made with timing specified in Timing Set 0.
Accesses made with timing specified in Timing Set 1.
This bit determines the access timing specification for I/O Window 1 (see page 72).
7.2 System I/O Map 0–1 Start Address Low
Register Name: System I/O Map 0–1 Start Address Low
Index: 08h, 0Ch
Register Per: socket
Register Compatibility Type: 365
Bit 2 Bit 1 Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Start Address 7:0
RW:00000000
There are two separate System I/O Map Start Address Low registers, each with identical fields. These
registers are located at the following indexes:
Index
System I/O Map Start Address Low
8h
Ch
System I/O Map 0 Start Address Low
System I/O Map 1 Start Address Low
Bits 7:0 — Start Address 7:0
This register contains the least-significant byte of the address that specifies the beginning of the
I/O space within the corresponding I/O map. I/O accesses that are equal or above this address
and equal or below the corresponding System I/O Map End Address will be mapped into the I/O
space of the corresponding PC Card.
The most-significant byte is located in the System I/O Map 0–1 Start Address High register (see
page 50).
7.3 System I/O Map 0–1 Start Address High
Register Name: System I/O Map 0–1 Start Address High
Index: 09h, 0Dh
Register Per: socket
Register Compatibility Type: 365
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Start Address 15:8
RW:00000000
There are two separate System I/O Map Start Address High registers, each with identical fields. These
registers are located at the following indexes:
Index
System I/O Map Start Address High
9h
Dh
System I/O Map 0 Start Address High
System I/O Map 1 Start Address High
Bits 15:8 — Start Address 15:8
This register contains the most-significant byte of the Start Address. See the description of the Start
Address field associated with bits 7:0 of the System I/O Map 0–1 Start Address Low register.
50
May 1997
I/O WINDOW MAPPING REGISTERS
PRELIMINARY DATA SHEET v3.1
CIRRUS [ CIRRUS LOGIC ]
