CL-PD6710/’22
ISA–to–PC-Card Host Adapters
6.5 Card Status Change
Register Name: Card Status Change
Index: 04h
Register Per: socket
Register Compatibility Type: 365
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Battery
Warning
Change
Battery Dead
Or Status
Change
Card Detect
Change
Ready
Change
0
0
0
0
R:0
R:0
R:0
R:0
R:0
R:0
R:0
R:0
This register indicates the source of a management interrupt generated by the CL-PD67XX.
NOTE: The corresponding bit in the Management Interrupt Configuration register must be set to ‘1’ to enable
each specific status change detection.
Bit 0 — Battery Dead Or Status Change
0
A transition (from high to low for memory card support or either high to low or low to high for I/O card
support) on the BVD1/-STSCHG pin has not occurred since this register was last read.
1
A transition on the BVD1/-STSCHG pin has occurred.
When the socket is configured for memory card support, this bit is set to ‘1’ when a BVD1 battery
dead high-to-low transition has been detected.When the socket is configured for I/O card support,
this bit is set to ‘1’ when the BVD1/-STSCHG pin (see page 19) changes from either high to low
or low to high. This bit is reset to ‘0’ whenever this register is read. In I/O Card Interface mode,
function of this bit is not affected by bit 7 of the Interrupt and General Control register.
Bit 1 — Battery Warning Change
0
1
A transition (from high to low) on the BVD2 pin has not occurred since this register was last read.
A transition on the BVD2 pin has occurred.
When a socket is configured for memory card support, this bit is set to ‘1’ when a high-to-low tran-
sition on BVD2 occurs indicating a battery warning was detected.This bit should be ignored when
the socket is configured for I/O card support. This bit is reset to ‘0’ whenever this register is read.
Bit 2 — Ready Change
0
A transition on the RDY/-IREQ pin has not occurred since this register was last read.
A transition on the RDY/-IREQ pin has occurred.
1
When this bit is ‘1’, a change has occurred in the card RDY/-IREQ pin (see page 17). This bit will
always read 0 when the card is configured as an I/O card.This bit is reset to ‘0’ whenever this reg-
ister is read.
Bit 3 — Card Detect Change
0
1
A transition on the -CD1 or -CD2 pins has not occurred since this register was last read.
A transition on the -CD1 or -CD2 pins has occurred.
When this bit is ‘1’, a change has occurred on the -CD1 or -CD2 pins (see page 18). This bit is
reset to ‘0’ whenever this register is read.
44
May 1997
CHIP CONTROL REGISTERS
PRELIMINARY DATA SHEET v3.1
CIRRUS [ CIRRUS LOGIC ]
