CAT28F010
(1)
Figure 7. Programming Algorithm
START
PROGRAMMING
BUS
OPERATION
COMMAND
COMMENTS
RAMPS TO V
V
APPLY V
PPH
PP
(OR V
PPH
STANDBY
HARDWIRED)
PP
INITIALIZE
ADDRESS
INITIALIZE ADDRESS
INITIALIZE PULSE COUNT
PLSCNT = PULSE COUNT
PLSCNT = 0
WRITE SETUP
PROG. COMMAND
1ST WRITE
CYCLE
WRITE
SETUP
DATA = 40H
WRITE PROG. CMD
ADDR AND DATA
2ND WRITE
CYCLE
PROGRAM VALID ADDRESS AND DATA
TIME OUT 10µs
WAIT
WRITE PROGRAM
VERIFY COMMAND
1ST WRITE
CYCLE
PROGRAM
DATA = C0H
VERIFY
TIME OUT 6µs
WAIT
READ DATA
FROM DEVICE
READ BYTE TO VERIFY
PROGRAMMING
READ
NO
INC
PLSCNT
= 25 ?
NO
VERIFY
DATA ?
COMPARE DATA OUTPUT
TO DATA EXPECTED
STANDBY
YES
YES
LAST
ADDRESS?
NO
INCREMENT
ADDRESS
YES
DATA = 00H
SETS THE REGISTER FOR
READ OPERATION
WRITE READ
COMMAND
1ST WRITE
CYCLE
READ
V
RAMPS TO V
APPLY V
PPL
APPLY V
PPL
PP
(OR V
PPL
STANDBY
HARDWIRED)
PP
PROGRAMMING
COMPLETED
PROGRAM
ERROR
Note:
(1) The algorithm MUST BE FOLLOWED to ensure proper and reliable operation of the device.
5108 FHD F06
Doc. No. 25005-0A 2/98 F-1
12
CATALYST [ CATALYST SEMICONDUCTOR ]
