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CAT28F010 参数 Datasheet PDF下载

CAT28F010图片预览
型号: CAT28F010
PDF下载: 下载PDF文件 查看货源
内容描述: 1兆位的CMOS闪存 [1 Megabit CMOS Flash Memory]
分类和应用: 闪存
文件页数/大小: 14 页 / 104 K
品牌: CATALYST [ CATALYST SEMICONDUCTOR ]
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CAT28F010  
Erase Mode  
Erase-Verify Mode  
During the first Write cycle, the command 20H is written  
into the command register. In order to commence the  
eraseoperation, theidenticalcommandof20Hhastobe  
written again into the register. This two-step process  
ensures against accidental erasure of the memory con-  
tents. The final erase cycle will be stopped at the rising  
edge of WE, at which time the Erase Verify command  
(A0H)issenttothecommandregister. Duringthiscycle,  
the address to be verified is sent to the address bus and  
latched when WE goes low. An integrated stop timer  
allows for automatic timing control over this operation,  
eliminating the need for a maximum erase timing speci-  
fication. Refer to AC Characteristics (Program/Erase)  
for specific timing parameters.  
The Erase-verify operation is performed on every byte  
after each erase pulse to verify that the bits have been  
erased.  
Programming Mode  
The programming operation is initiated using the pro-  
gramming algorithm of Figure 7. During the first write  
cycle, the command 40H is written into the command  
register. During the second write cycle, the address of  
thememorylocationtobeprogrammedislatchedonthe  
falling edge of WE, while the data is latched on the rising  
edge of WE. The program operation terminates with the  
next rising edge of WE. An integrated stop timer allows  
forautomatictimingcontroloverthisoperation, eliminat-  
ing the need for a maximum program timing specifica-  
tion. Refer to AC Characteristics (Program/Erase) for  
specific timing parameters.  
Figure 6. A.C. Timing for Programming Operation  
SETUP PROGRAM LATCH ADDRESS  
POWER-UP  
PROGRAM  
VERIFY  
COMMAND  
PROGRAM  
VERIFICATION  
V
POWER-DOWN/  
STANDBY  
V
CC  
CC  
& STANDBY  
COMMAND  
& DATA  
PROGRAMMING  
ADDRESSES  
t
t
t
WC  
WC  
RC  
t
t
AS  
AH  
CE (E)  
t
t
CH  
CS  
t
t
CH  
EHQZ  
t
t
CS  
CH  
OE (G)  
t
GHWL  
t
t
t
WHGL  
DF  
WHWH1  
t
WPH  
WE (W)  
t
t
t
t
WP  
WP  
WP  
OE  
t
t
t
t
DH  
DH  
DH  
OH  
t
t
t
t
DS  
DS  
OLZ  
DS  
HIGH-Z  
DATA IN  
= 40H  
DATA IN  
= C0H  
DATA (I/O)  
DATA IN  
VALID  
DATA OUT  
t
LZ  
t
CE  
5.0V  
0V  
V
CC  
t
VPEL  
V
V
PPH  
PPL  
V
PP  
28F010 F08  
Doc. No. 25005-0A 2/98 F-1  
11  
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