CAT28F010
(1)
Figure 5. Chip Erase Algorithm
BUS
OPERATION
START ERASURE
COMMAND
COMMENTS
RAMPS TO V
V
PP
(OR V
PPH
APPLY V
PPH
HARDWIRED)
PP
ALL BYTES SHALL BE
PROGRAMMED TO 00
BEFORE AN ERASE
OPERATION
PROGRAM ALL
BYTES TO 00H
STANDBY
INITIALIZE
ADDRESS
INITIALIZE ADDRESS
INITIALIZE
PLSCNT = 0
PLSCNT = PULSE COUNT
ACTUAL ERASE
WRITE ERASE
SETUP COMMAND
WRITE
WRITE
ERASE
ERASE
NEEDS 10ms PULSE,
DATA = 20H
DATA = 20H
WRITE ERASE
COMMAND
DATA = 20H
WAIT
TIME OUT 10ms
ADDRESS = BYTE TO VERIFY
WRITE ERASE
VERIFY COMMAND
ERASE
VERIFY
40H;
WRITE
DATA = 20H;
A0H
STOPS ERASE OPERATION
TIME OUT 6µs
WAIT
INCREMENT
ADDRESS
READ DATA
FROM DEVICE
READ
READ BYTE TO
VERIFY ERASURE
NO
NO
DATA =
FFH?
INC PLSCNT
1000
= 3000 ?
COMPARE OUTPUT TO FF
INCREMENT PULSE COUNT
STANDBY
YES
YES
LAST
NO
ADDRESS?
YES
DATA = 00H
RESETS THE REGISTER
FOR READ OPERATION
WRITE READ
COMMAND
WRITE
READ
V
RAMPS TO V
PPL
PP
(OR V
APPLY V
PPL
APPLY V
PPL
STANDBY
HARDWIRED)
PP
ERASURE
COMPLETED
ERASE
ERROR
Note:
(1) The algorithm MUST BE FOLLOWED to ensure proper and reliable operation of the device.
5108 FHD F10
Doc. No. 25005-0A 2/98 F-1
10
CATALYST [ CATALYST SEMICONDUCTOR ]
