CAT24WC257
I2C BUS PROTOCOL
The features of the I2C bus protocol are defined as
follows:
many as four devices on the same bus. These bits must
compare to their hardwired input pins. The last bit of the
slave address specifies whether a Read or Write opera-
tion is to be performed. When this bit is set to 1, a Read
operation is selected, and when set to 0, a Write opera-
tion is selected.
(1) Data transfer may be initiated only when the bus is
not busy.
(2) During a data transfer, the data line must remain
stablewhenevertheclocklineishigh.Anychanges
in the data line while the clock line is high will be
interpreted as a START or STOP condition.
After the Master sends a START condition and the slave
address byte, the CAT24WC257 monitors the bus and
responds with an acknowledge (on the SDA line) when
its address matches the transmitted slave address. The
CAT24WC257 then performs a Read or Write operation
depending on the state of the R/W bit.
START Condition
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of
SDA when SCL is HIGH. The CAT24WC257 monitors
the SDA and SCL lines and will not respond until this
condition is met.
Acknowledge
Afterasuccessfuldatatransfer, eachreceivingdeviceis
requiredtogenerateanacknowledge.TheAcknowledg-
ing device pulls down the SDA line during the ninth clock
cycle, signaling that it received the 8 bits of data.
STOP Condition
A LOW to HIGH transition of SDA when SCL is HIGH
determinestheSTOPcondition.Alloperationsmustend
with a STOP condition.
TheCAT24WC257respondswithanacknowledgeafter
receivingaSTARTconditionanditsslaveaddress. Ifthe
device has been selected along with a write operation,
it responds with an acknowledge after receiving each 8-
bit byte.
DEVICE ADDRESSING
The bus Master begins a transmission by sending a
START condition. The Master sends the address of the
particular slave device it is requesting. The five most
significant bits of the 8-bit slave address are fixed as
10100(Fig. 5). The CAT24WC257 uses the next two bits
as address bits. The address bits A1 and A0 allow as
When the CAT24WC257 begins a READ mode it trans-
mits 8 bits of data, releases the SDA line, and monitors
the line for an acknowledge. Once it receives this ac-
knowledge, the CAT24WC257 will continue to transmit
data. IfnoacknowledgeissentbytheMaster, thedevice
Figure 4. Acknowledge Timing
SCL FROM
MASTER
1
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACKNOWLEDGE
Figure 5. Slave Address Bits
1
0
1
0
0
A1
A0 R/W
Doc. No. 1030, Rev. E
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