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CAT1163WI-25 参数 Datasheet PDF下载

CAT1163WI-25图片预览
型号: CAT1163WI-25
PDF下载: 下载PDF文件 查看货源
内容描述: 监控电路,带有I2C串行串行EEPROM CMOS ,精密复位控制器和看门狗定时器 [Supervisory Circuits with I2C Serial Serial CMOS EEPROM, Precision Reset Controller and Watchdog Timer]
分类和应用: 外围集成电路光电二极管监控控制器可编程只读存储器电动程控只读存储器电可擦编程只读存储器
文件页数/大小: 14 页 / 151 K
品牌: CATALYST [ CATALYST SEMICONDUCTOR ]
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CAT1163  
D.C. OPERATING CHARACTERISTICS  
VCC = 2.7V to 6.0V, unless otherwise specified.  
Symbol Parameter  
Test Conditions  
fSCL = 100kHz  
VCC = 3.3V  
Min  
Typ  
Max  
Units  
mA  
µA  
µA  
µA  
µA  
V
ICC  
Power Supply Current  
3
40  
50  
ISB  
Standby Current  
VCC = 5V  
ILI  
ILO  
Input Leakage Current  
Output Leakage Current  
Input Low Voltage  
VIN = GND or VCC  
VIN = GND or VCC  
2
10  
VIL  
-1  
VCC x 0.3  
VCC + 0.5  
0.4  
VIH  
VOL1  
Input High Voltage  
VCC x 0.7  
V
Output Low Voltage (SDA)  
IOL = 3 mA, VCC = 3.0V  
V
CAPACITANCE  
TA = 25ºC, f = 1.0MHz, VCC = 5V  
Symbol  
Test  
Conditions  
VI/O = 0V  
VIN = 0V  
Max  
8
Units  
pF  
(1)  
CI/O  
Input/Output Capacitance (SDA)  
Input Capacitance (SCL)  
(1)  
CIN  
6
pF  
A.C. CHARACTERISTICS  
CC = 2.7V to 6.0V unless otherwise specified. Output Load is 1 TTL Gate and 100pF.  
cc = 2.7V - 6V Vcc = 4.5V – 5.5V  
V
V
Symbol Parameter  
Units  
kHz  
ns  
Min  
Max  
100  
200  
3.5  
Min  
Max  
400  
200  
1
FSCL  
TI(1)  
tAA  
Clock Frequency  
Noise Suppresion Time Constant at SCL, SDA Inputs  
SLC Low to SDA Data Out and ACK Out  
µs  
Time the Bus Must be Free Before a New Transmission  
Can Start  
(1)  
tBUF  
4.7  
1.2  
µs  
tHD:STA  
tLOW  
Start Condition Hold Time  
Clock Low Period  
4
4.7  
4
0.6  
1.2  
0.6  
0.6  
0
µs  
µs  
µs  
µs  
ns  
ns  
µs  
ns  
µs  
ns  
tHIGH  
Clock High Period  
tSU:STA  
tHD:DAT  
tSU:DAT  
Start Condition Setup Time (for a Repeated Start Condition)  
Data in Hold Time  
4.7  
0
Data in Setup Time  
50  
50  
(1)  
tR  
SDA and SCL Rise Time  
SDA and SCL Fall Time  
Stop Condition Setup Time  
Data Out Hold Time  
1
0.3  
(1)  
tF  
300  
300  
tSU:STO  
tDH  
4
0.6  
100  
100  
POWER-UP TIMING (1)(2)  
Symbol Parameter  
Max  
Units  
ms  
tPUR  
tPUW  
Power-up to Read Operation  
Power-up to Write Operation  
1
1
ms  
Notes:  
(1) This parameter is tested initially and after a design or process change that affects the parameter.  
(2) tPUR and tPUW are the delays required from the time VCC is stable until the specific operation can be initiated.  
© 2007 Catalyst Semiconductor, Inc.  
Characteristics subject to change without notice  
3
Doc. No. 3003 Rev. E