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CAT1163WI-25 参数 Datasheet PDF下载

CAT1163WI-25图片预览
型号: CAT1163WI-25
PDF下载: 下载PDF文件 查看货源
内容描述: 监控电路,带有I2C串行串行EEPROM CMOS ,精密复位控制器和看门狗定时器 [Supervisory Circuits with I2C Serial Serial CMOS EEPROM, Precision Reset Controller and Watchdog Timer]
分类和应用: 外围集成电路光电二极管监控控制器可编程只读存储器电动程控只读存储器电可擦编程只读存储器
文件页数/大小: 14 页 / 151 K
品牌: CATALYST [ CATALYST SEMICONDUCTOR ]
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CAT1163  
BLOCK DIAGRAM  
RESET THRESHOLD OPTION  
EXTERNAL LOAD  
Part Dash  
Number  
Minimum  
Threshold  
Maximum  
Threshold  
SENSEAMPS  
SHIFT REGISTERS  
D
OUT  
ACK  
V
CC  
-45  
-42  
-30  
-28  
-25  
4.50  
4.25  
3.00  
2.85  
2.55  
4.75  
4.50  
3.15  
3.00  
2.70  
WORDADDRESS  
BUFFERS  
COLUMN  
DECODERS  
GND  
START/STOP  
LOGIC  
SDA  
EEPROM  
XDEC  
CONTROL  
LOGIC  
WP  
DATA IN STORAGE  
HIGHVOLTAGE/  
TIMING CONTROL  
RESET Controller  
STATE COUNTERS  
SCL  
Precision  
SLAVE  
WATCHDOG  
ADDRESS  
COMPARATORS  
Vcc Monitor  
WDI RESET RESET  
ABSOLUTE MAXIMUM RATINGS(1)  
Parameters  
Ratings  
–55 to +125  
–65 to +150  
–2.0 to VCC + 2.0  
–2.0 to 7.0  
1.0  
Units  
ºC  
ºC  
V
Temperature Under Bias  
Storage Temperature  
Voltage on any Pin with Respect to Ground(2)  
VCC with Respect to Ground  
V
Package Power Dissipation Capability (TA = 25°C)  
Lead Soldering Temperature (10 secs)  
Output Short Circuit Current(3)  
W
300  
ºC  
mA  
100  
REABILITY CHARACTERISTICS  
Symbol  
Parameter  
Reference Test Method  
Min  
Max  
Units  
Cycles/Byte  
Years  
(4)  
NEND  
Endurance  
MIL-STD-883, Test Method 1033  
MIL-STD-883, Test Method 1008  
MIL-STD-883, Test Method 3015  
JEDEC Standard 17  
1,000,000  
100  
(4)  
TDR  
Data Retention  
ESD Susceptibility  
Latch-up  
(4)  
VZAP  
2000  
Volts  
(4)(5)  
ILTH  
100  
mA  
Notes:  
(1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings  
only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this  
specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.  
(2) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20ns. Maximum DC  
voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns.  
(3) Output shorted for no more than one second. No more than one output shorted at a time.  
(4) This parameter is tested initially and after a design or process change that affects the parameter.  
(5) Latch-up protection is provided for stresses up to 100mA on address and data pins from –1V to VCC +1V.  
Doc. No. 3003 Rev. E  
2
© 2007 Catalyst Semiconductor, Inc.  
Characteristics subject to change without notice