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CAT1163WI-25 参数 Datasheet PDF下载

CAT1163WI-25图片预览
型号: CAT1163WI-25
PDF下载: 下载PDF文件 查看货源
内容描述: 监控电路,带有I2C串行串行EEPROM CMOS ,精密复位控制器和看门狗定时器 [Supervisory Circuits with I2C Serial Serial CMOS EEPROM, Precision Reset Controller and Watchdog Timer]
分类和应用: 外围集成电路光电二极管监控控制器可编程只读存储器电动程控只读存储器电可擦编程只读存储器
文件页数/大小: 14 页 / 151 K
品牌: CATALYST [ CATALYST SEMICONDUCTOR ]
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CAT1163  
Acknowledge Polling  
READ OPERATIONS  
Disabling of the inputs can be used to take  
advantage of the typical write cycle time. Once the  
stop condition is issued to indicate the end of the  
host’s write opration, the CAT1163 initiates the  
internal write cycle. ACK polling can be initiated  
immediately. This involves issuing the start condition  
followed by the slave address for a write operation. If  
the CAT1163 is still busy with the write operation, no  
ACK will be returned. If a write operation has  
completed, an ACK will be returned and the host can  
then proceed with the next read or write operation.  
The READ operation for the CAT1163 is initiated in the  
same manner as the write operation with one exception,  
¯¯  
that R/W bit is set to one. Three different READ ope–  
rations are possible: Immediate/Current Address READ,  
Selective/Random READ and Sequential READ.  
Immediate/Current Address Read  
The CAT1163’s address counter contains the address  
of the last byte accessed, incremented by one. In other  
words, if the last READ or WRITE access was to  
address N, the READ immediately following would  
access data from address N+1. For all devices,  
N=E=2047. The counter will wrap around to Zero and  
continue to clock out valid data for the 16K devices.  
After the CAT1163 receives its slave address  
WRITE PROTECTION  
The Write Protection feature allows the user to  
protect against inadvertent memory array program-  
ming. If the WP pin is tied to VCC, the entire memory  
array is protected and becomes read only. The  
CAT1163 will accept both slave and byte addresses,  
but the memory location accessed is protected from  
programming by the device’s failure to send an  
acknowledge after the first byte of data is received.  
¯¯  
information (with the R/W bit set to one), it issues an  
acknowledge, then transmits the 8-bit byte requested.  
The master device does not send an acknowledge, but  
will generate a STOP condition.  
Figure 9. Immediate Address Read Timing  
S
T
A
R
T
S
T
O
P
BUS ACTIVIT Y:  
MASTER  
SLAVE  
ADDRESS  
SDA LINE  
S
P
A
C
K
N
O
DATA  
A
C
K
SCL  
SDA  
8
9
8TH BIT  
DATA OUT  
NO ACK  
STOP  
© 2007 Catalyst Semiconductor, Inc.  
Characteristics subject to change without notice  
9
Doc. No. 3003 Rev. E