Preliminary Information
CAT1024, CAT1025
DEVICE OPERATION
Reset Controller Description
The CAT1024/25 precision RESET controllers ensure
correct system operation during brownout and power
up/down conditions. They are configured with open
drain RESET outputs.
including write operations. If the Reset output(s) are
active, in progress communications to the EEPROM are
aborted and no new communications are allowed. In this
conditionaninternalwritecycletothememorycannotbe
started, but an in progress internal non-volatile memory
write cycle can not be aborted. An internal write cycle
initiated before the Reset condition can be successfully
finishedifthereisenoughtime(5ms)beforeVCCreaches
the minimum value of 2V.
During power-up, the RESET outputs remain active
until VCC reaches the VTH threshold and will continue
driving the outputs for approximately 200ms (tPURST
)
after reaching VTH. After the tPURST timeout interval, the
device will cease to drive the reset outputs. At this point
the reset outputs will be pulled up or down by their
respective pull up/down resistors.
In addition, the CAT1025 includes a Write Protection Input
which when tied to VCC will disable any write operations
to the device.
During power-down, the RESET outputs will be active
when VCC falls below VTH. The RESET output will be
valid so long as VCC is >1.0V (VRVALID). The device is
designedtoignorethefastnegativegoingVCC transient
pulses (glitches).
Reset output timing is shown in Figure 1.
Manual Reset Operation
TheRESET pincanoperateasresetoutputandmanual
reset input. The input is edge triggered; that is, the
RESET input will initiate a reset timeout after detecting
a high to low transition.
When RESET I/O is driven to the active state, the 200
msectimerwillbegintotimetheresetinterval. Ifexternal
reset is shorter than 200 ms, Reset outputs will remain
active at least 200 ms.
CAT1024/25 also have a separate manual reset input.
Driving the MR input low by connecting a pushbutton
(normally open) from MR pin to GND will generate a
reset condition. The input has a internal pull up resistor.
Reset remains asserted while MR is low and for the
Reset Timeout period after MR input has gone high.
Glitches shorter than 100 ns on MR input will not
generate a reset pulse. No external debouncing circuits
are required. Manual reset operation using MR input is
shown in Figure 2.
Hardware Data Protection
The CAT1024/25 family has been designed to solve
many of the data corruption issues that have long been
associatedwithserialEEPROMs. Datacorruptionoccurs
whenincorrectdataisstoredinamemorylocationwhich
is assumed to hold correct data.
Whenever the device is in a Reset condition, the
embedded EEPROM is disabled for all operations,
Doc No. 3008, Rev. G
7
CATALYST [ CATALYST SEMICONDUCTOR ]
